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64-bit tx system risc tx49 family tmpr4955a

r4000/r4400/r5000 are a trademark of mips technologies, inc. the information contained herein is subject to change without notice. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. the products described in this document contain components made in the united states and subject to export control of the u.s. authorities. diversion contrary to the u.s. law is prohibited. toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications ( computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. the products described in this document may include products subject to the foreign exchange and foreign trade laws. ? 2001 toshiba corporation
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preface thank you for your new or continued patronage of toshiba semiconductor products. this is the 2001 edition of the user?s manual for the tmpr4955a 64-bit risc microprocessor. this databook is written so as to be accessible to engineers who may be designing a toshiba microprocessor into their products for the first time. no prior knowledge of this device is assumed. what we offer here is basic information about the microprocessor, a discussion of the application fields in which the microprocessor is utilized, and an overview of design methods. on the other hand, the more experienced designer will find complete technical specifications for this product. toshiba continually updates its technical information. your comments and suggestions concerning this and other toshiba documents are sincerely appreciated and may be utilized in subsequent editions. for updating of the data in this manual, or for additional information about the product appearing in it, please contact your nearest toshiba office or authorized toshiba dealer. dec 2000

tmpr4955a i contents handling precautions tmpr4955a chapter 1. introduction ......................................................................................................... ................... 1-1 1.1 overview .................................................................................................................... .................... 1-1 1.2 notation used in this manual ................................................................................................ ....... 1-1 1.2.1 numerical notation ........................................................................................................ ........ 1-1 1.2.2 data notation............................................................................................................. ............. 1-1 1.2.3 signal notation ........................................................................................................... ............ 1-1 1.2.4 register notation ......................................................................................................... ........... 1-1 chapter 2. features ............................................................................................................. ..................... 2-1 2.1 block diagram ............................................................................................................... ................ 2-2 2.2 pin description ............................................................................................................. ................. 2-3 2.2.1 tx4955a pin out (160-pin qfp)............................................................................................ 2 -3 chapter 3. initialization interface............................................................................................. .............. 3-1 3.1 functional overview ......................................................................................................... ............ 3-1 3.1.1 system coordination....................................................................................................... ....... 3-1 3.2 reset signal description.................................................................................................... ........... 3-2 3.2.1 cold reset ................................................................................................................ ............... 3-2 3.2.2 warm reset................................................................................................................ ............. 3-2 3.3 tx4955a..................................................................................................................... .................... 3-4 3.3.1 power modes (doze/halt mode) ............................................................................................ 3- 4 3.3.2 operating modes ........................................................................................................... ......... 3-5 3.3.3 system endianness ......................................................................................................... ....... 3-5 3.3.4 reverse endianness ........................................................................................................ ....... 3-6 3.3.5 instruction trace support ................................................................................................. .... 3-6 3.3.6 bootstrap exception vector ................................................................................................ ... 3-6 3.3.7 interrupt enable .......................................................................................................... .......... 3-6 3.3.8 floating-point reigsters .................................................................................................. ...... 3-6 chapter 4. clock interface...................................................................................................... .................. 4-1 4.1 signal terminology.......................................................................................................... .............. 4-1 4.2 basic system clocks......................................................................................................... ............. 4-2 4.2.1 masterclock............................................................................................................... ............. 4-2 4.2.2 pclock .................................................................................................................... ................. 4-2 4.2.3 sclock .................................................................................................................... ................. 4-2 4.2.4 pclock-to-sclock division ................................................................................................. .... 4-3 4.2.5 phase-locked loop (pll) ................................................................................................... ... 4-3 4.3 connecting clocks to a phase-locked system ............................................................................ 4-4 chapter 5 cache organization.................................................................................................... ............ 5-1 5.1 memory organization ......................................................................................................... .......... 5-1 5.2 cache organization .......................................................................................................... ............. 5-2 5.2.1 cache sizes ............................................................................................................... .............. 5-2 5.2.2 cache line lengths ........................................................................................................ ....... 5-2 5.2.3 organization of the instruction cache (i-cache) ................................................................. 5-2 5.2.4 instruction cache address field........................................................................................... ... 5-3 5.2.5 instruction cache configuration........................................................................................... .. 5-3 5.2.6 organization of the data cache (d-cache) .......................................................................... 5-4 5.2.7 data cache address field .................................................................................................. ...... 5-4 5.2.8 data cache configuration .................................................................................................. ..... 5-4 5.3 lock function ............................................................................................................... .................. 5-5 5.3.1 lock function ............................................................................................................. ............. 5-5 5.3.2 operation during lock ..................................................................................................... ....... 5-6 5.3.3 example of data cache locking............................................................................................. .5-6
tmpr4955a ii 5.3.4 example of instruction cache locking ................................................................................... 5-6 5.4 the primary cache accessing ................................................................................................. ....... 5-7 5.5 cache states ................................................................................................................ .................. 5-7 5.6 cache line ownership ........................................................................................................ .......... 5-8 5.7 cache multi-hit operation ................................................................................................... ........ 5-8 5.8 fifo replacement algorithm .................................................................................................. .... 5-8 5.9 cache testing............................................................................................................... .................. 5-9 5.9.1 cache disabling ........................................................................................................... ........... 5-9 5.9.2 cache flushing............................................................................................................ ........... 5-9 5.10 cache operations ........................................................................................................... ............. 5-10 5.10.1 cache write policy ....................................................................................................... .........5-11 5.10.2 data cache line replacement .............................................................................................5 -11 5.10.3 instruction cache line replacement.................................................................................. 5-12 5.11 manipulation of the caches by an external agent ................................................................... 5-12 chapter 6. tx4955a system interface ............................................................................................. ....... 6-1 6.1 terminology ................................................................................................................. .................. 6-1 6.2 explanation of system interface of r5000 type protocol mode .................................................. 6-1 6.2.1 interface bus ............................................................................................................. .............. 6-2 6.2.2 address cycle and data cycle .............................................................................................. ... 6-2 6.2.3 issue cycle ............................................................................................................... ................ 6-3 6.2.4 handshake signal.......................................................................................................... ......... 6-4 6.2.5 system interface protocol of r5000 type .............................................................................. 6-4 6.2.5.1 master state and slave state.......................................................................................... 6- 5 6.2.5.2 shifting from the master state to the slave state ........................................................ 6-5 6.2.5.3 external arbitration .................................................................................................... ... 6-5 6.2.5.4 shifting to the slave state on its own............................................................................ 6-5 6.2.6 processor requests and external requests ......................................................................... 6-6 6.2.6.1 rules relating to processor requests ............................................................................. 6-6 6.2.6.2 processor requests...................................................................................................... .... 6-7 6.2.6.3 processor read requests ................................................................................................. 6-7 6.2.6.4 processor write request................................................................................................. .6-8 6.2.6.5 external requests ....................................................................................................... .... 6-8 6.2.6.6 external read requests.................................................................................................. .6-9 6.2.6.7 external write requests ................................................................................................. 6-9 6.2.6.8 read responses .......................................................................................................... ... 6-10 6.2.7 handling of requests ...................................................................................................... ..... 6-10 6.2.7.1 load miss ............................................................................................................... ....... 6-10 6.2.7.2 store miss .............................................................................................................. ....... 6-10 6.2.7.3 store hits.............................................................................................................. ..........6-11 6.2.7.4 uncached load or store.................................................................................................. 6-11 6.2.7.5 cache instruction operation .........................................................................................6-11 6.2.8 processor request and external request protocol ............................................................ 6-12 6.2.8.1 processor request protocol ........................................................................................... 6-1 2 6.2.8.2 processor read request protocol................................................................................... 6-12 6.2.8.3 processor write request protocols................................................................................ 6-13 6.2.8.4 processor single write requests ................................................................................... 6-15 6.2.8.5 processor block write request ...................................................................................... 6-17 6.2.8.6 external request protocol ............................................................................................ 6-1 7 6.2.8.7 external arbitration protocol....................................................................................... 6-18 6.2.8.8 external read request protocol .................................................................................... 6-19 6.2.8.9 external null request protocol..................................................................................... 6-20 6.2.8.10 external write request protocol................................................................................... 6-21 6.2.8.11 read response protocol ................................................................................................ 6 -22 6.2.9 data transfer ............................................................................................................. .......... 6-24 6.2.9.1 data transfer pattern................................................................................................... 6-24 6.2.9.2 independent transfer on sysad bus ........................................................................... 6-24 6.2.10 system interface cycle time.............................................................................................. ... 6-25 6.2.10.1 release latency ........................................................................................................ ..... 6-25
tmpr4955a iii 6.2.11 system interface command and data identifiers ............................................................. 6-26 6.2.11.1 syntax of commands and data identifiers .................................................................. 6-26 6.2.11.2 syntax of system interface commands........................................................................ 6-26 6.2.11.3 read requests .......................................................................................................... ..... 6-27 6.2.11.4 write requests ......................................................................................................... ..... 6-28 6.2.11.5 null requests .......................................................................................................... ...... 6-29 6.2.11.6 syntax of system interface data identifiers................................................................ 6-29 6.2.11.7 non-coherent data...................................................................................................... .. 6-29 6.2.11.8 bit definition of data identifiers .................................................................................. 6-3 0 6.2.12 system interface addresses............................................................................................... .. 6-31 6.2.12.1 addressing rules in the 32-bit bus mode .................................................................... 6-31 6.2.13 mode register of system interface (g2sconfig)................................................................. 6-31 6.2.14 data error detection ..................................................................................................... ...... 6-32 6.2.14.1 indication of good data by data identifier syscmd(5) ............................................... 6-32 6.2.14.2 determination by a check bit ...................................................................................... 6-32 6.2.14.3 timing at which a bus error exception occurs............................................................ 6-32 6.2.14.4 precautions ............................................................................................................ ....... 6-32 6.3 system interface of tx4300 type protocol mode ....................................................................... 6-33 6.3.1 system interface description of tx4300 type protocol mode .......................................... 6-33 6.3.2 system events ............................................................................................................. ......... 6-35 6.3.3 system event sequences and the sysad bus protocol ..................................................... 6-35 6.3.3.1 fetch miss.............................................................................................................. ....... 6-35 6.3.3.2 load miss............................................................................................................... ....... 6-36 6.3.3.3 store miss .............................................................................................................. ....... 6-36 6.3.3.4 uncached load or store............................................................................................... 6-3 6 6.3.3.5 cache instructions ...................................................................................................... .6-36 6.3.3.6 byte ordering (endian) ............................................................................................... 6-3 6 6.3.3.7 physical addresses ...................................................................................................... .6-36 6.3.3.8 interface buses......................................................................................................... .... 6-36 6.3.3.9 address and data cycles ............................................................................................. 6-37 6.3.4 system interface protocols ................................................................................................ .. 6-38 6.3.4.1 master and slave states .............................................................................................. 6-3 8 6.3.4.2 moving from master to slave state ............................................................................ 6-38 6.3.4.3 external arbitration .................................................................................................... 6-39 6.3.4.4 uncompelled change to slave state ........................................................................... 6-39 6.3.4.5 signal timing ........................................................................................................... .... 6-39 6.3.5 timing summary ............................................................................................................ ..... 6-40 6.3.6 arbitration ............................................................................................................... ............. 6-45 6.3.7 issuing commands.......................................................................................................... ..... 6-46 6.3.8 processor write request ................................................................................................... ... 6-46 6.3.9 processor read request.................................................................................................... ... 6-48 6.3.10 external write request ................................................................................................... .... 6-48 6.3.11 external read response ................................................................................................... ... 6-50 6.3.12 flow control ............................................................................................................. ............ 6-52 6.3.13 data rate control ........................................................................................................ ........ 6-53 6.3.14 consecutive sysad bus transactions ................................................................................ 6-54 6.3.15 starvation and deadlock avoidance.................................................................................... 6-56 6.3.16 discarding and re-executing read command .................................................................. 6-56 6.3.17 multiple drivers on the sysad bus.................................................................................... 6-57 6.3.18 signal codes ............................................................................................................. ............ 6-58 6.3.19 physical addresses ....................................................................................................... ........ 6-60 6.3.20 mode register of system interface (g2sconfig)................................................................ 6-60 6.3.21 read time out counter (mode43 * = 0)............................................................................ 6-61 chapter 7. jtag interface ....................................................................................................... ................ 7-1 7.1 what boundary scanning is................................................................................................... ...... 7-1 7.2 signal summary .............................................................................................................. .............. 7-2 7.3 jtag controller and registers ............................................................................................... ..... 7-3 7.3.1 instruction register ...................................................................................................... ......... 7-3
tmpr4955a iv 7.3.2 bypass register ........................................................................................................... ........... 7-4 7.3.3 boundary-scan register .................................................................................................... .... 7-5 7.3.4 device identification register ............................................................................................ ... 7-5 7.3.5 test access port (tap) .................................................................................................... ....... 7-6 7.3.6 tap controller............................................................................................................ ............ 7-6 7.3.7 controller reset .......................................................................................................... ........... 7-6 7.3.8 tap controller............................................................................................................ ............ 7-7 7.4 instructions for jtag ....................................................................................................... ...........7-11 7.4.1 the extest instruction.................................................................................................... ..7-11 7.4.2 the sample/preload instruction................................................................................. 7-12 7.4.3 the bypass instruction .................................................................................................... .7-13 7.4.4 the idcode instruction.................................................................................................... .7-13 7.5 note ........................................................................................................................ ...................... 7-14 chapter 8. tx4955a processor interrupts ......................................................................................... ..... 8-1 8.1 nonmaskable interrupt ....................................................................................................... ......... 8-1 8.2 external interrupts ......................................................................................................... .............. 8-1 8.3 software interrupt .......................................................................................................... .............. 8-1 8.4 timer interrupt ............................................................................................................. ................ 8-2 8.5 asserting interrupts........................................................................................................ .............. 8-3 chapter 9. debug support unit ................................................................................................... ............ 9-1 9.1 features .................................................................................................................... ..................... 9-1 9.2 ejtag interface ............................................................................................................. ............... 9-1 9.3 jtag interface .............................................................................................................. ................ 9-2 9.4 processor access overview ................................................................................................... ........ 9-2 9.5 instruction ................................................................................................................. .................... 9-2 9.6 debug unit.................................................................................................................. ................... 9-3 9.6.1 extended instructions..................................................................................................... ....... 9-3 9.6.2 extended debug registers in cp0 ........................................................................................ 9-3 9.7 register map................................................................................................................ .................. 9-3 9.8 processor bus break function ................................................................................................ ..... 9-3 9.9 debug exception............................................................................................................. ............... 9-4 9.9.1 debug single step (dss) ................................................................................................... .... 9-4 9.9.2 debug breakpoint exception (dbp) ....................................................................................... 9-4 9.9.3 jtag break exception ...................................................................................................... .... 9-4 9.9.4 debug exception handling.................................................................................................. .. 9-4 9.9.5 branching to debug handler ................................................................................................ .. 9-4 9.9.6 exception handling when in debug mode (dm bit is set) ................................................... 9-4 9.10 real time pc trace output .................................................................................................. .... 9-4 chapter 10. electrical characteristics .......................................................................................... .......... 10-1 10.1 electrical characteristics of tmpr4955af............................................................................... 10-1 10.1.1 absolute maximum ratings ................................................................................................ 1 0-1 10.1.2 recommended operating conditions.................................................................................. 10-1 10.1.3 dc characteristics ....................................................................................................... ........ 10-2 10.1.4 ac characteristics ....................................................................................................... ........ 10-2 10.1.4.1 clock timing........................................................................................................... ...... 10-2 10.1.4.2 system interface ....................................................................................................... ... 10-2 10.1.5 timing diagrams.......................................................................................................... ........ 10-3 10.1.5.1 clock timing........................................................................................................... ...... 10-3 10.1.5.2 pclock to sclock divisor of 2 .................................................................................. 10-3 10.1.5.3 system interface timing ............................................................................................. 10- 4 10.1.5.4 cold reset timing ...................................................................................................... .. 10-4 10.1.5.5 warm reset timing...................................................................................................... 10-4 chapter 11. package dimension ................................................................................................... ............11-1 a. pll passive components ....................................................................................................... ..............a-1 b. movement parameter setting of a processor.................................................................................... ....b-1
tmpr4955a v c. differences between the tmpr4955 and the tmpr4955a ...............................................................c-1
tmpr4955a vi
handling precautions

1 using toshiba semiconductors safely 1-1 1. using toshiba semiconductors safely toshiba are continually working to improve the quality and the reliability of their products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a toshiba product could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent products specifications. also, please keep in mind the precautions and conditions set forth in the toshiba semiconductor reliability handbook.
1 using toshiba semiconductors safely 1-2
2 safety precautions 2-1 2. safety precautions this section lists important precautions which users of semiconductor devices (and anyone else) should observe in order to avoid injury and damage to property, and to ensure safe and correct use of devices. please be sure that you understand the meanings of the labels and the graphic symbol described below before you move on to the detailed descriptions of the precautions. [explanation of labels] [explanation of labels] [explanation of labels] [explanation of labels] indicates an imminently hazardous situation which will result in death or serious injury if you do not follow instructions. indicates a potentially hazardous situation which could result in death or serious injury if you do not follow instructions. indicates a potentially hazardous situation which if not avoided, may result in minor injury or moderate injury. [explanation of graphic symbol] [explanation of graphic symbol] [explanation of graphic symbol] [explanation of graphic symbol] graphic symbol meaning indicates that caution is required (laser beam is dangerous to eyes).
2 safety precautions 2-2 2.1 general precautions regarding semiconductor devices do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature). this may cause the device to break down, degrade its performance, or cause it to catch fire or explode resulting in injury. do not insert devices in the wrong orientation. make sure that the positive and negative terminals of power supplies are connected correctly. otherwise the rated maximum current or power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to catch fire or explode and resulting in injury. when power to a device is on, do not touch the device?s heat sink. heat sinks become hot, so you may burn your hand. do not touch the tips of device leads. because some types of device have leads with pointed tips, you may prick your finger. when conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment?s electrodes or probes to the pins of the device under test before powering it on. otherwise, you may receive an electric shock causing injury. before grounding an item of measuring equipment or a soldering iron, check that there is no electrical leakage from it. electrical leakage may cause the device which you are testing or soldering to break down, or could give you an electric shock. always wear protective glasses when cutting the leads of a device with clippers or a similar tool. if you do not, small bits of metal flying off the cut ends may damage your eyes.
2 safety precautions 2-3 2.2 precautions specific to each product group 2.2.1 optical semiconductor devices when a visible semiconductor laser is operating, do not look directly into the laser beam or look through the optical system. this is highly likely to impair vision, and in the worst case may cause blindness. if it is necessary to examine the laser apparatus, for example to inspect its optical characteristics, always wear the appropri ate type of laser protective glasses as stipulated by iec standard iec825-1. ensure that the current flowing in an led device does not exceed the device?s maximum rated current. this is particularly important for resin-packaged led devices, as excessive current may cause the package resin to blow up, scattering resin fragments and causing injury. when testing the dielectric strength of a photocoupler, use testing equipment which can shut off the supply voltage to the photocoupler. if you detect a leakage current of more than 100 2.2.2 power devices never touch a power device while it is powered on. also, after turning off a power device, do not touch it until it has thoroug hly discharged all remaining electrical charge. touching a power device while it is powered on or still charged could cause a severe electric shock, resulting in death or seri ous injury. when conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment?s electrodes or probes to the device under test before powering it on. when you have finished, discharge any electrical charge remaining in the device. connecting the electrodes or probes of testing equipment to a device while it is powered on may result in electric shock, causi ng injury.
2 safety precautions 2-4 do not use devices under conditions which exceed their absolute maximum ratings (current, voltage, power dissipation, temperature etc.). this may cause the device to break down, causing a large short-circuit current to flow, which may in turn cause it to catch fir e or explode, resulting in fire or injury. use a unit which can detect short-circuit currents and which will shut off the power supply if a short-circuit occurs. if the power supply is not shut off, a large short-circuit current will flow continuously, which may in turn cause the device t o catch fire or explode, resulting in fire or injury. when designing a case for enclosing your system, consider how best to protect the user from shrapnel in the event of the device catching fire or exploding. flying shrapnel can cause injury. when conducting any kind of evaluation, inspection or testing, always use protective safety tools such as a cover for the devic e. otherwise you may sustain injury caused by the device catching fire or exploding. make sure that all metal casings in your design are grounded to earth. even in modules where a device?s electrodes and metal casing are insulated, capacitance in the module may cause the electrostatic potential in the casing to rise. dielectric breakdown may cause a high voltage to be applied to the casing, causing electric shock and injury to anyone touching it. when designing the heat radiation and safety features of a system incorporating high-speed rectifiers, remember to take the device?s forward and reverse losses into account. the leakage current in these devices is greater than that in ordinary rectifiers; as a result, if a high-speed rectifier is use d in an extreme environment (e.g. at high temperature or high voltage), its reverse loss may increase, causing thermal runaway to occur . this may in turn cause the device to explode and scatter shrapnel, resulting in injury to the user. a design should ensure that, except when the main circuit of the device is active, reverse bias is applied to the device gate w hile electricity is conducted to control circuits, so that the main circuit will become inactive. malfunction of the device may cause serious accidents or injuries. when conducting any kind of evaluation, inspection or testing, either wear protective gloves or wait until the device has coole d properly before handling it. devices become hot when they are operated. even after the power has been turned off, the device will retain residual heat which may cause a burn to anyone touching it. 2.2.3 bipolar ics (for use in automobiles) if your design includes an inductive load such as a motor coil, incorporate diodes or similar devices into the design to preven t negative current from flowing in. the load current generated by powering the device on and off may cause it to function erratically or to break down, which could in turn cause injury. ensure that the power supply to any device which incorporates protective functions is stable. if the power supply is unstable, the device may operate erratically, preventing the protective functions from working correctly . if protective functions fail, the device may break down causing injury to the user.
3 general safety precautions and usage considerations 3-1 3. general safety precautions and usage considerations this section is designed to help you gain a better understanding of semiconductor devices, so as to ensure the safety, quality and reliability of the devices which you incorporate into your designs. 3.1 from incoming to shipping 3.1.1 electrostatic discharge (esd) when handling individual devices (which are not yet mounted on a printed circuit board), be sure that the environment is protected against electrostatic electricity. operators should wear anti-static clothing, and containers and other objects which come into direct contact with devices should be made of anti-static materials and should be grounded to earth via an 0.5- to 1.0-m ? protective resistor. please follow the precautions described below; this is particularly important for devices which are marked ?be careful of static.?. (1) work environment ? when humidity in the working environment decreases, the human body and other insulators can easily become charged with static electricity due to friction. maintain the recommended humidity of 40% to 60% in the work environment, while also taking into account the fact that moisture-proof-packed products may absorb moisture after unpacking. ? be sure that all equipment, jigs and tools in the working area are grounded to earth. ? place a conductive mat over the floor of the work area, or take other appropriate measures, so that the floor surface is protected against static electricity and is grounded to earth. the surface resistivity should be 10 4 to 10 8 ? /sq and the resistance between surface and ground, 7.5 10 5 to 10 8 ? ? cover the workbench surface also with a conductive mat (with a surface resistivity of 10 4 to 10 8 ? /sq, for a resistance between surface and ground of 7.5 10 5 to 10 8 ? ) . the purpose of this is to disperse static electricity on the surface (through resistive components) and ground it to earth. workbench surfaces must not be constructed of low-resistance metallic materials that allow rapid static discharge when a charged device touches them directly. ? pay attention to the following points when using automatic equipment in your workplace: (a) when picking up ics with a vacuum unit, use a conductive rubber fitting on the end of the pick-up wand to protect against electrostatic charge. (b) minimize friction on ic package surfaces. if some rubbing is unavoidable due to the device?s mechanical structure, minimize the friction plane or use material with a small friction coefficient and low electrical resistance. also, consider the use of an ionizer. (c) in sections which come into contact with device lead terminals, use a material which dissipates static electricity. (d) ensure that no statically charged bodies (such as work clothes or the human body) touch the devices.
3 general safety precautions and usage considerations 3-2 (e) make sure that sections of the tape carrier which come into contact with installation devices or other electrical machinery are made of a low-resistance material. (f) make sure that jigs and tools used in the assembly process do not touch devices. (g) in processes in which packages may retain an electrostatic charge, use an ionizer to neutralize the ions. ? make sure that crt displays in the working area are protected against static charge, for example by a vdt filter. as much as possible, avoid turning displays on and off. doing so can cause electrostatic induction in devices. ? keep track of charged potential in the working area by taking periodic measurements. ? ensure that work chairs are protected by an anti-static textile cover and are grounded to the floor surface by a grounding chain. (suggested resistance between the seat surface and grounding chain is 7.5 10 5 to 10 12 ? .) ? install anti-static mats on storage shelf surfaces. (suggested surface resistivity is 10 4 to 10 8 ? /sq; suggested resistance between surface and ground is 7.5 10 5 to 10 8 ? .) ? for transport and temporary storage of devices, use containers (boxes, jigs or bags) that are made of anti-static materials or materials which dissipate electrostatic charge. ? make sure that cart surfaces which come into contact with device packaging are made of materials which will conduct static electricity, and verify that they are grounded to the floor surface via a grounding chain. ? in any location where the level of static electricity is to be closely controlled, the ground resistance level should be class 3 or above. use different ground wires for all items of equipment which may come into physical contact with devices. (2) operating environment ? operators must wear anti-static clothing and conductive shoes (or a leg or heel strap). ? operators must wear a wrist strap grounded to earth via a resistor of about 1 m ? . ? soldering irons must be grounded from iron tip to earth, and must be used only at low voltages (6 v to 24 v). ? if the tweezers you use are likely to touch the device terminals, use anti-static tweezers and in particular avoid metallic tweezers. if a charged device touches a low-resistance tool, rapid discharge can occur. when using vacuum tweezers, attach a conductive chucking pat to the tip, and connect it to a dedicated ground used especially for anti-static purposes (suggested resistance value: 10 4 to 10 8 ? ). ? do not place devices or their containers near sources of strong electrical fields (such as above a crt).
3 general safety precautions and usage considerations 3-3 ? when storing printed circuit boards which have devices mounted on them, use a board container or bag that is protected against static charge. to avoid the occurrence of static charge or discharge due to friction, keep the boards separate from one other and do not stack them directly on top of one another. ? ensure, if possible, that any articles (such as clipboards) which are brought to any location where the level of static electricity must be closely controlled are constructed of anti-static materials. ? in cases where the human body comes into direct contact with a device, be sure to wear anti- static finger covers or gloves (suggested resistance value: 10 8 ? or less). ? equipment safety covers installed near devices should have resistance ratings of 10 9 ? or less. ? if a wrist strap cannot be used for some reason, and there is a possibility of imparting friction to devices, use an ionizer. ? the transport film used in tcp products is manufactured from materials in which static charges tend to build up. when using these products, install an ionizer to prevent the film from being charged with static electricity. also, ensure that no static electricity will be applied to the product?s copper foils by taking measures to prevent static occuring in the peripheral equipment. 3.1.2 vibration, impact and stress handle devices and packaging materials with care. to avoid damage to devices, do not toss or drop packages. ensure that devices are not subjected to mechanical vibration or shock during transportation. ceramic package devices and devices in canister-type packages which have empty space inside them are subject to damage from vibration and shock because the bonding wires are secured only at their ends. plastic molded devices, on the other hand, have a relatively high level of resistance to vibration and mechanical shock because their bonding wires are enveloped and fixed in resin. however, when any device or package type is installed in target equipment, it is to some extent susceptible to wiring disconnections and other damage from vibration, shock and stressed solder junctions. therefore when devices are incorporated into the design of equipment which will be subject to vibration, the structural design of the equipment must be thought out carefully. if a device is subjected to especially strong vibration, mechanical shock or stress, the package or the chip itself may crack. in products such as ccds which incorporate window glass, this could cause surface flaws in the glass or cause the connection between the glass and the ceramic to separate. furthermore, it is known that stress applied to a semiconductor device through the package changes the resistance characteristics of the chip because of piezoelectric effects. in analog circuit design attention must be paid to the problem of package stress as well as to the dangers of vibration and shock as described above. vibration
3 general safety precautions and usage considerations 3-4 3.2 storage 3.2.1 general storage ? avoid storage locations where devices will be exposed to moisture or direct sunlight. ? follow the instructions printed on the device cartons regarding transportation and storage. ? the storage area temperature should be kept within a temperature range of 5c to 35c, and relative humidity should be maintained at between 45% and 75%. ? do not store devices in the presence of harmful (especially corrosive) gases, or in dusty conditions. ? use storage areas where there is minimal temperature fluctuation. rapid temperature changes can cause moisture to form on stored devices, resulting in lead oxidation or corrosion. as a result, the solderability of the leads will be degraded. ? when repacking devices, use anti-static containers. ? do not allow external forces or loads to be applied to devices while they are in storage. ? if devices have been stored for more than two years, their electrical characteristics should be tested and their leads should be tested for ease of soldering before they are used. 3.2.2 moisture-proof packing moisture-proof packing should be handled with care. the handling procedure specified for each packing type should be followed scrupulously. if the proper procedures are not followed, the quality and reliability of devices may be degraded. this section describes general precautions for handling moisture-proof packing. since the details may differ from device to device, refer also to the relevant individual datasheets or databook. (1) general precautions follow the instructions printed on the device cartons regarding transportation and storage. ? do not drop or toss device packing. the laminated aluminum material in it can be rendered ineffective by rough handling. ? the storage area temperature should be kept within a temperature range of 5c to 30c, and relative humidity should be maintained at 90% (max). use devices within 12 months of the date marked on the package seal. yy humidity: temperature:
3 general safety precautions and usage considerations 3-5 ? if the 12-month storage period has expired, or if the 30% humidity indicator shown in figure 1 is pink when the packing is opened, it may be advisable, depending on the device and packing type, to back the devices at high temperature to remove any moisture. please refer to the table below. after the pack has been opened, use the devices in a 5 c to 30 c. 60% rh environment and within the effective usage period listed on the moisture-proof package. if the effective usage period has expired, or if the packing has been stored in a high-humidity environment, bake the devices at high temperature. packing moisture removal tray if the packing bears the ?heatproof? marking or indicates the maximum temperature which it can withstand, bake at 125 ? when baking devices, protect the devices from static electricity. ? moisture indicators can detect the approximate humidity level at a standard temperature of 25 c. 6-point indicators and 3-point indicators are currently in use, but eventually all indicators will be 3-point indicators. danger if pink change desiccant read at lavender between pink & blue 10% 20% 30% 40% 50% 60% humidity indicator danger if pink read at lavender between pink & blue 20 30 40 humidity indicator (a) 6-point indicator (b) 3-point indicator figure 1 humidity indicator
3 general safety precautions and usage considerations 3-6 3.3 design care must be exercised in the design of electronic equipment to achieve the desired reliability. it is important not only to adhere to specifications concerning absolute maximum ratings and recommended operating conditions, it is also important to consider the overall environment in which equipment will be used, including factors such as the ambient temperature, transient noise and voltage and current surges, as well as mounting conditions which affect device reliability. this section describes some general precautions which you should observe when designing circuits and when mounting devices on printed circuit boards. for more detailed information about each product family, refer to the relevant individual technical datasheets available from toshiba. 3.3.1 absolute maximum ratings do not use devices under conditions in which their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature) will be exceeded. a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. the absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. although absolute maximum ratings differ from product to product, they essentially concern the voltage and current at each pin, the allowable power dissipation, and the junction and storage temperatures. if the voltage or current on any pin exceeds the absolute maximum rating, the device?s internal circuitry can become degraded. in the worst case, heat generated in internal circuitry can fuse wiring or cause the semiconductor chip to break down. if storage or operating temperatures exceed rated values, the package seal can deteriorate or the wires can become disconnected due to the differences between the thermal expansion coefficients of the materials from which the device is constructed. 3.3.2 recommended operating conditions the recommended operating conditions for each device are those necessary to guarantee that the device will operate as specified in the datasheet. if greater reliability is required, derate the device?s absolute maximum ratings for voltage, current, power and temperature before using it. 3.3.3 derating when incorporating a device into your design, reduce its rated absolute maximum voltage, current, power dissipation and operating temperature in order to ensure high reliability. since derating differs from application to application, refer to the technical datasheets available for the various devices used in your design. 3.3.4 unused pins if unused pins are left open, some devices can exhibit input instability problems, resulting in malfunctions such as abrupt increase in current flow. similarly, if the unused output pins on a device are connected to the power supply pin, the ground pin or to other output pins, the ic may malfunction or break down.
3 general safety precautions and usage considerations 3-7 since the details regarding the handling of unused pins differ from device to device and from pin to pin, please follow the instructions given in the relevant individual datasheets or databook. cmos logic ic inputs, for example, have extremely high impedance. if an input pin is left open, it can easily pick up extraneous noise and become unstable. in this case, if the input voltage level reaches an intermediate level, it is possible that both the p-channel and n-channel transistors will be turned on, allowing unwanted supply current to flow. therefore, ensure that the unused input pins of a device are connected to the power supply (vcc) pin or ground (gnd) pin of the same device. for details of what to do with the pins of heat sinks, refer to the relevant technical datasheet and databook. 3.3.5 latch-up latch-up is an abnormal condition inherent in cmos devices, in which vcc gets shorted to ground. this happens when a parasitic pn-pn junction (thyristor structure) internal to the cmos chip is turned on, causing a large current of the order of several hundred ma or more to flow between vcc and gnd, eventually causing the device to break down. latch-up occurs when the input or output voltage exceeds the rated value, causing a large current to flow in the internal chip, or when the voltage on the vcc (vdd) pin exceeds its rated value, forcing the internal chip into a breakdown condition. once the chip falls into the latch-up state, even though the excess voltage may have been applied only for an instant, the large current continues to flow between vcc (vdd) and gnd (vss). this causes the device to heat up and, in extreme cases, to emit gas fumes as well. to avoid this problem, observe the following precautions: (1) do not allow voltage levels on the input and output pins either to rise above vcc (vdd) or to fall below gnd (vss). also, follow any prescribed power-on sequence, so that power is applied gradually or in steps rather than abruptly. (2) do not allow any abnormal noise signals to be applied to the device. (3) set the voltage levels of unused input pins to vcc (vdd) or gnd (vss). (4) do not connect output pins to one another. 3.3.6 input/output protection wired-and configurations, in which outputs are connected together, cannot be used, since this short-circuits the outputs. outputs should, of course, never be connected to vcc (vdd) or gnd (vss). furthermore, ics with tri-state outputs can undergo performance degradation if a shorted output current is allowed to flow for an extended period of time. therefore, when designing circuits, make sure that tri-state outputs will not be enabled simultaneously. 3.3.7 load capacitance some devices display increased delay times if the load capacitance is large. also, large charging and discharging currents will flow in the device, causing noise. furthermore, since outputs are shorted for a relatively long time, wiring can become fused. consult the technical information for the device being used to determine the recommended load capacitance.
3 general safety precautions and usage considerations 3-8 3.3.8 thermal design the failure rate of semiconductor devices is greatly increased as operating temperatures increase. as shown in figure 2, the internal thermal stress on a device is the sum of the ambient temperature and the temperature rise due to power dissipation in the device. therefore, to achieve optimum reliability, observe the following precautions concerning thermal design: (1) keep the ambient temperature (ta) as low as possible. (2) if the device?s dynamic power dissipation is relatively large, select the most appropriate circuit board material, and consider the use of heat sinks or of forced air cooling. such measures will help lower the thermal resistance of the package. (3) derate the device?s absolute maximum ratings to minimize thermal stress from power dissipation. ja = jc + ca ja = (tj?ta) / p jc = (tj?tc) / p ca = (tc?ta) / p in which ja = thermal resistance between junction and surrounding air (c/w) jc = thermal resistance between junction and package surface, or internal thermal resistance (c/w) ca = thermal resistance between package surface and surrounding air, or external thermal resistance (c/w) tj = junction temperature or chip temperature (c) tc = package surface temperature or case temperature (c) ta = ambient temperature (c) p = power dissipation (w) tc figure 2 thermal resistance of package 3.3.9 interfacing when connecting inputs and outputs between devices, make sure input voltage (v il /v ih ) and output voltage (v ol /v oh ) levels are matched. otherwise, the devices may malfunction. when connecting devices operating at different supply voltages, such as in a dual-power-supply system, be aware that erroneous power-on and power-off sequences can result in device breakdown. for details of how to interface particular devices, consult the relevant technical datasheets and databooks. if you have any questions or doubts about interfacing, contact your nearest toshiba office or distributor.
3 general safety precautions and usage considerations 3-9 3.3.10 decoupling spike currents generated during switching can cause vcc (vdd) and gnd (vss) voltage levels to fluctuate, causing ringing in the output waveform or a delay in response speed. (the power supply and gnd wiring impedance is normally 50 ? to 100 ? .) for this reason, the impedance of power supply lines with respect to high frequencies must be kept low. this can be accomplished by using thick and short wiring for the vcc (vdd) and gnd (vss) lines and by installing decoupling capacitors (of approximately 0.01 f to 1 f capacitance) as high-frequency filters between vcc (vdd) and gnd (vss) at strategic locations on the printed circuit board. for low-frequency filtering, it is a good idea to install a 10- to 100- f capacitor on the printed circuit board (one capacitor will suffice). if the capacitance is excessively large, however, (e.g. several thousand f) latch-up can be a problem. be sure to choose an appropriate capacitance value. an important point about wiring is that, in the case of high-speed logic ics, noise is caused mainly by reflection and crosstalk, or by the power supply impedance. reflections cause increased signal delay, ringing, overshoot and undershoot, thereby reducing the device?s safety margins with respect to noise. to prevent reflections, reduce the wiring length by increasing the device mounting density so as to lower the inductance (l) and capacitance (c) in the wiring. extreme care must be taken, however, when taking this corrective measure, since it tends to cause crosstalk between the wires. in practice, there must be a trade-off between these two factors. 3.3.11 external noise printed circuit boards with long i/o or signal pattern lines are vulnerable to induced noise or surges from outside sources. consequently, malfunctions or breakdowns can result from overcurrent or overvoltage, depending on the types of device used. to protect against noise, lower the impedance of the pattern line or insert a noise-canceling circuit. protective measures must also be taken against surges. for details of the appropriate protective measures for a particular device, consult the relevant databook. 3.3.12 electromagnetic interference widespread use of electrical and electronic equipment in recent years has brought with it radio and tv reception problems due to electromagnetic interference. to use the radio spectrum effectively and to maintain radio communications quality, each country has formulated regulations limiting the amount of electromagnetic interference which can be generated by individual products. electromagnetic interference includes conduction noise propagated through power supply and telephone lines, and noise from direct electromagnetic waves radiated by equipment. different measurement methods and corrective measures are used to assess and counteract each specific type of noise. difficulties in controlling electromagnetic interference derive from the fact that there is no method available which allows designers to calculate, at the design stage, the strength of the electromagnetic waves which will emanate from each component in a piece of equipment. for this reason, it is only after the prototype equipment has been completed that the designer can take measurements using a dedicated instrument to determine the strength of electromagnetic interference waves. yet it is possible during system design to incorporate some measures for the prevention of electromagnetic interference, which can facilitate taking corrective measures once the design has been completed. these include installing shields and noise filters, and increasing input/output signals
3 general safety precautions and usage considerations 3-10 the thickness of the power supply wiring patterns on the printed circuit board. one effective method, for example, is to devise several shielding options during design, and then select the most suitable shielding method based on the results of measurements taken after the prototype has been completed. 3.3.13 peripheral circuits in most cases semiconductor devices are used with peripheral circuits and components. the input and output signal voltages and currents in these circuits must be chosen to match the semiconductor device?s specifications. the following factors must be taken into account. (1) inappropriate voltages or currents applied to a device?s input pins may cause it to operate erratically. some devices contain pull-up or pull-down resistors. when designing your system, remember to take the effect of this on the voltage and current levels into account. (2) the output pins on a device have a predetermined external circuit drive capability. if this drive capability is greater than that required, either incorporate a compensating circuit into your design or carefully select suitable components for use in external circuits. 3.3.14 safety standards each country has safety standards which must be observed. these safety standards include requirements for quality assurance systems and design of device insulation. such requirements must be fully taken into account to ensure that your design conforms to the applicable safety standards. 3.3.15 other precautions (1) when designing a system, be sure to incorporate fail-safe and other appropriate measures according to the intended purpose of your system. also, be sure to debug your system under actual board-mounted conditions. (2) if a plastic-package device is placed in a strong electric field, surface leakage may occur due to the charge-up phenomenon, resulting in device malfunction. in such cases take appropriate measures to prevent this problem, for example by protecting the package surface with a conductive shield. (3) with some microcomputers and mos memory devices, caution is required when powering on or resetting the device. to ensure that your design does not violate device specifications, consult the relevant databook for each constituent device. (4) ensure that no conductive material or object (such as a metal pin) can drop onto and short the leads of a device mounted on a printed circuit board. 3.4 inspection, testing and evaluation 3.4.1 grounding ground all measuring instruments, jigs, tools and soldering irons to earth. electrical leakage may cause a device to break down or may result in electric shock.
3 general safety precautions and usage considerations 3-11 3.4.2 inspection sequence c do not insert devices in the wrong orientation. make sure that the positive and negative electrodes of the power supply are correctly connected. otherwise, the rated maximum current or maximum power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to catch fire or explode, resulting in injury to the user. d when conducting any kind of evaluation, inspection or testing using ac power with a peak voltage of 42.4 v or dc power exceeding 60 v, be sure to connect the electrodes or probes of the testing equipment to the device under test before powering it on. connecting the electrodes or probes of testing equipment to a device while it is powered on may result in electric shock, causing injury. (1) apply voltage to the test jig only after inserting the device securely into it. when applying or removing power, observe the relevant precautions, if any. (2) make sure that the voltage applied to the device is off before removing the device from the test jig. otherwise, the device may undergo performance degradation or be destroyed. (3) make sure that no surge voltages from the measuring equipment are applied to the device. (4) the chips housed in tape carrier packages (tcps) are bare chips and are therefore exposed. during inspection take care not to crack the chip or cause any flaws in it. electrical contact may also cause a chip to become faulty. therefore make sure that nothing comes into electrical contact with the chip. 3.5 mounting there are essentially two main types of semiconductor device package: lead insertion and surface mount. during mounting on printed circuit boards, devices can become contaminated by flux or damaged by thermal stress from the soldering process. with surface-mount devices in particular, the most significant problem is thermal stress from solder reflow, when the entire package is subjected to heat. this section describes a recommended temperature profile for each mounting method, as well as general precautions which you should take when mounting devices on printed circuit boards. note, however, that even for devices with the same package type, the appropriate mounting method varies according to the size of the chip and the size and shape of the lead frame. therefore, please consult the relevant technical datasheet and databook. 3.5.1 lead forming c always wear protective glasses when cutting the leads of a device with clippers or a similar tool. if you do not, small bits of metal flying off the cut ends may damage your eyes. d do not touch the tips of device leads. because some types of device have leads with pointed tips, you may prick your finger. semiconductor devices must undergo a process in which the leads are cut and formed before the devices can be mounted on a printed circuit board. if undue stress is applied to the interior of a device during this process, mechanical breakdown or performance degradation can result. this is attributable primarily to differences between the stress on the device?s external leads and the stress on the internal leads. if the relative difference is great enough, the device?s internal leads, adhesive properties or sealant can be damaged. observe these precautions during the lead- forming process (this does not apply to surface-mount devices):
3 general safety precautions and usage considerations 3-12 (1) lead insertion hole intervals on the printed circuit board should match the lead pitch of the device precisely. (2) if lead insertion hole intervals on the printed circuit board do not precisely match the lead pitch of the device, do not attempt to forcibly insert devices by pressing on them or by pulling on their leads. (3) for the minimum clearance specification between a device and a printed circuit board, refer to the relevant device?s datasheet and databook. if necessary, achieve the required clearance by forming the device?s leads appropriately. do not use the spacers which are used to raise devices above the surface of the printed circuit board during soldering to achieve clearance. these spacers normally continue to expand due to heat, even after the solder has begun to solidify; this applies severe stress to the device. (4) observe the following precautions when forming the leads of a device prior to mounting. ? use a tool or jig to secure the lead at its base (where the lead meets the device package) while bending so as to avoid mechanical stress to the device. also avoid bending or stretching device leads repeatedly. ? be careful not to damage the lead during lead forming. ? follow any other precautions described in the individual datasheets and databooks for each device and package type. 3.5.2 socket mounting (1) when socket mounting devices on a printed circuit board, use sockets which match the inserted device?s package. (2) use sockets whose contacts have the appropriate contact pressure. if the contact pressure is insufficient, the socket may not make a perfect contact when the device is repeatedly inserted and removed; if the pressure is excessively high, the device leads may be bent or damaged when they are inserted into or removed from the socket. (3) when soldering sockets to the printed circuit board, use sockets whose construction prevents flux from penetrating into the contacts or which allows flux to be completely cleaned off. (4) make sure the coating agent applied to the printed circuit board for moisture-proofing purposes does not stick to the socket contacts. (5) if the device leads are severely bent by a socket as it is inserted or removed and you wish to repair the leads so as to continue using the device, make sure that this lead correction is only performed once. do not use devices whose leads have been corrected more than once. (6) if the printed circuit board with the devices mounted on it will be subjected to vibration from external sources, use sockets which have a strong contact pressure so as to prevent the sockets and devices from vibrating relative to one another. 3.5.3 soldering temperature profile the soldering temperature and heating time vary from device to device. therefore, when specifying the mounting conditions, refer to the individual datasheets and databooks for the devices used.
3 general safety precautions and usage considerations 3-13 (1) using a soldering iron complete soldering within ten seconds for lead temperatures of up to 260c, or within three seconds for lead temperatures of up to 350c. (2) using medium infrared ray reflow ? heating top and bottom with long or medium infrared rays is recommended (see figure 3). long infrared ray heater (preheating) medium infrared ray heater (reflow) product flow figure 3 heating top and bottom with long or medium infrared rays ? complete the infrared ray reflow process within 30 seconds at a package surface temperature of between 210c and 240c. ? refer to figure 4 for an example of a good temperature profile for infrared or hot air reflow. 210 30 s or less time (s) 60-120 s (c) 240 160 140 package surface temperature figure 4 sample temperature profile for infrared or hot air reflow (3) using hot air reflow ? complete hot air reflow within 30 seconds at a package surface temperature of between 210c and 240c. ? for an example of a recommended temperature profile, refer to figure 4 above. (4) using solder flow ? apply preheating for 60 to 120 seconds at a temperature of 150c. ? for lead insertion-type packages, complete solder flow within 10 seconds with the temperature at the stopper (or, if there is no stopper, at a location more than 1.5 mm from the body) which does not exceed 260c.
3 general safety precautions and usage considerations 3-14 ? for surface-mount packages, complete soldering within 5 seconds at a temperature of 250c or less in order to prevent thermal stress in the device. ? figure 5 shows an example of a recommended temperature profile for surface-mount packages using solder flow. 5 s or less 60-120 s (c) 250 160 140 package surface temperature time (s) figure 5 sample temperature profile for solder flow 3.5.4 flux cleaning and ultrasonic cleaning (1) when cleaning circuit boards to remove flux, make sure that no residual reactive ions such as na or cl remain. note that organic solvents react with water to generate hydrogen chloride and other corrosive gases which can degrade device performance. (2) washing devices with water will not cause any problems. however, make sure that no reactive ions such as sodium and chlorine are left as a residue. also, be sure to dry devices sufficiently after washing. (3) do not rub device markings with a brush or with your hand during cleaning or while the devices are still wet from the cleaning agent. doing so can rub off the markings. (4) the dip cleaning, shower cleaning and steam cleaning processes all involve the chemical action of a solvent. use only recommended solvents for these cleaning methods. when immersing devices in a solvent or steam bath, make sure that the temperature of the liquid is 50c or below, and that the circuit board is removed from the bath within one minute. (5) ultrasonic cleaning should not be used with hermetically-sealed ceramic packages such as a leadless chip carrier (lcc), pin grid array (pga) or charge-coupled device (ccd), because the bonding wires can become disconnected due to resonance during the cleaning process. even if a device package allows ultrasonic cleaning, limit the duration of ultrasonic cleaning to as short a time as possible, since long hours of ultrasonic cleaning degrade the adhesion between the mold resin and the frame material. the following ultrasonic cleaning conditions are recommended: frequency: 27 khz 29 khz ultrasonic output power: 300 w or less (0.25 w/cm 2 or less) cleaning time: 30 seconds or less suspend the circuit board in the solvent bath during ultrasonic cleaning in such a way that the ultrasonic vibrator does not come into direct contact with the circuit board or the device.
3 general safety precautions and usage considerations 3-15 3.5.5 no cleaning if analog devices or high-speed devices are used without being cleaned, flux residues may cause minute amounts of leakage between pins. similarly, dew condensation, which occurs in environments containing residual chlorine when power to the device is on, may cause between- lead leakage or migration. therefore, toshiba recommends that these devices be cleaned. however, if the flux used contains only a small amount of halogen (0.05w% or less), the devices may be used without cleaning without any problems. 3.5.6 mounting tape carrier packages (tcps) (1) when tape carrier packages (tcps) are mounted, measures must be taken to prevent electrostatic breakdown of the devices. (2) if devices are being picked up from tape, or outer lead bonding (olb) mounting is being carried out, consult the manufacturer of the insertion machine which is being used, in order to establish the optimum mounting conditions in advance and to avoid any possible hazards. (3) the base film, which is made of polyimide, is hard and thin. be careful not to cut or scratch your hands or any objects while handling the tape. (4) when punching tape, try not to scatter broken pieces of tape too much. (5) treat the extra film, reels and spacers left after punching as industrial waste, taking care not to destroy or pollute the environment. (6) chips housed in tape carrier packages (tcps) are bare chips and therefore have their reverse side exposed. to ensure that the chip will not be cracked during mounting, ensure that no mechanical shock is applied to the reverse side of the chip. electrical contact may also cause a chip to fail. therefore, when mounting devices, make sure that nothing comes into electrical contact with the reverse side of the chip. if your design requires connecting the reverse side of the chip to the circuit board, please consult toshiba or a toshiba distributor beforehand. 3.5.7 mounting chips devices delivered in chip form tend to degrade or break under external forces much more easily than plastic-packaged devices. therefore, caution is required when handling this type of device. (1) mount devices in a properly prepared environment so that chip surfaces will not be exposed to polluted ambient air or other polluted substances. (2) when handling chips, be careful not to expose them to static electricity. in particular, measures must be taken to prevent static damage during the mounting of chips. with this in mind, toshiba recommend mounting all peripheral parts first and then mounting chips last (after all other components have been mounted). (3) make sure that pcbs (or any other kind of circuit board) on which chips are being mounted do not have any chemical residues on them (such as the chemicals which were used for etching the pcbs). (4) when mounting chips on a board, use the method of assembly that is most suitable for maintaining the appropriate electrical, thermal and mechanical properties of the semiconductor devices used. * for details of devices in chip form, refer to the relevant device?s individual datasheets.
3 general safety precautions and usage considerations 3-16 3.5.8 circuit board coating when devices are to be used in equipment requiring a high degree of reliability or in extreme environments (where moisture, corrosive gas or dust is present), circuit boards may be coated for protection. however, before doing so, you must carefully consider the possible stress and contamination effects that may result and then choose the coating resin which results in the minimum level of stress to the device. 3.5.9 heat sinks (1) when attaching a heat sink to a device, be careful not to apply excessive force to the device in the process. (2) when attaching a device to a heat sink by fixing it at two or more locations, evenly tighten all the screws in stages (i.e. do not fully tighten one screw while the rest are still only loosely tightened). finally, fully tighten all the screws up to the specified torque. (3) drill holes for screws in the heat sink exactly as specified. smooth the surface by removing burrs and protrusions or indentations which might interfere with the installation of any part of the device. (4) a coating of silicone compound can be applied between the heat sink and the device to improve heat conductivity. be sure to apply the coating thinly and evenly; do not use too much. also, be sure to use a non-volatile compound, as volatile compounds can crack after a time, causing the heat radiation properties of the heat sink to deteriorate. (5) if the device is housed in a plastic package, use caution when selecting the type of silicone compound to be applied between the heat sink and the device. with some types, the base oil separates and penetrates the plastic package, significantly reducing the useful life of the device. two recommended silicone compounds in which base oil separation is not a problem are yg6260 from toshiba silicone. (6) heat-sink-equipped devices can become very hot during operation. do not touch them, or you may sustain a burn. 3.5.10 tightening torque (1) make sure the screws are tightened with fastening torques not exceeding the torque values stipulated in individual datasheets and databooks for the devices used. (2) do not allow a power screwdriver (electrical or air-driven) to touch devices. 3.5.11 repeated device mounting and usage do not remount or re-use devices which fall into the categories listed below; these devices may cause significant problems relating to performance and reliability. (1) devices which have been removed from the board after soldering (2) devices which have been inserted in the wrong orientation or which have had reverse current applied (3) devices which have undergone lead forming more than once
3 general safety precautions and usage considerations 3-17 3.6 protecting devices in the field 3.6.1 temperature semiconductor devices are generally more sensitive to temperature than are other electronic components. the various electrical characteristics of a semiconductor device are dependent on the ambient temperature at which the device is used. it is therefore necessary to understand the temperature characteristics of a device and to incorporate device derating into circuit design. note also that if a device is used above its maximum temperature rating, device deterioration is more rapid and it will reach the end of its usable life sooner than expected. 3.6.2 humidity resin-molded devices are sometimes improperly sealed. when these devices are used for an extended period of time in a high-humidity environment, moisture can penetrate into the device and cause chip degradation or malfunction. furthermore, when devices are mounted on a regular printed circuit board, the impedance between wiring components can decrease under high- humidity conditions. in systems which require a high signal-source impedance, circuit board leakage or leakage between device lead pins can cause malfunctions. the application of a moisture-proof treatment to the device surface should be considered in this case. on the other hand, operation under low-humidity conditions can damage a device due to the occurrence of electrostatic discharge. unless damp-proofing measures have been specifically taken, use devices only in environments with appropriate ambient moisture levels (i.e. within a relative humidity range of 40% to 60%). 3.6.3 corrosive gases corrosive gases can cause chemical reactions in devices, degrading device characteristics. for example, sulphur-bearing corrosive gases emanating from rubber placed near a device (accompanied by condensation under high-humidity conditions) can corrode a device?s leads. the resulting chemical reaction between leads forms foreign particles which can cause electrical leakage. 3.6.4 radioactive and cosmic rays most industrial and consumer semiconductor devices are not designed with protection against radioactive and cosmic rays. devices used in aerospace equipment or in radioactive environments must therefore be shielded. 3.6.5 strong electrical and magnetic fields devices exposed to strong magnetic fields can undergo a polarization phenomenon in their plastic material, or within the chip, which gives rise to abnormal symptoms such as impedance changes or increased leakage current. failures have been reported in lsis mounted near malfunctioning deflection yokes in tv sets. in such cases the device?s installation location must be changed or the device must be shielded against the electrical or magnetic field. shielding against magnetism is especially necessary for devices used in an alternating magnetic field because of the electromotive forces generated in this type of environment.
3 general safety precautions and usage considerations 3-18 3.6.6 interference from light (ultraviolet rays, sunlight, fluorescent lamps and incandescent lamps) light striking a semiconductor device generates electromotive force due to photoelectric effects. in some cases the device can malfunction. this is especially true for devices in which the internal chip is exposed. when designing circuits, make sure that devices are protected against incident light from external sources. this problem is not limited to optical semiconductors and eproms. all types of device can be affected by light. 3.6.7 dust and oil just like corrosive gases, dust and oil can cause chemical reactions in devices, which will adversely affect a device?s electrical characteristics. to avoid this problem, do not use devices in dusty or oily environments. this is especially important for optical devices because dust and oil can affect a device?s optical characteristics as well as its physical integrity and the electrical performance factors mentioned above. 3.6.8 fire semiconductor devices are combustible; they can emit smoke and catch fire if heated sufficiently. when this happens, some devices may generate poisonous gases. devices should therefore never be used in close proximity to an open flame or a heat-generating body, or near flammable or combustible materials. 3.7 disposal of devices and packing materials when discarding unused devices and packing materials, follow all procedures specified by local regulations in order to protect the environment against contamination.
4 precautions and usage considerations 4-1 4. precautions and usage considerations this section describes matters specific to each product group which need to be taken into consideration when using devices. if the same item is described in sections 3 and 4, the description in section 4 takes precedence. 4.1 microcontrollers 4.1.1 design (1) using resonators which are not specifically recommended for use resonators recommended for use with toshiba products in microcontroller oscillator applications are listed in toshiba databooks along with information about oscillation conditions. if you use a resonator not included in this list, please consult toshiba or the resonator manufacturer concerning the suitability of the device for your application. (2) undefined functions in some microcontrollers certain instruction code values do not constitute valid processor instructions. also, it is possible that the values of bits in registers will become undefined. take care in your applications not to use invalid instructions or to let register bit values become undefined.
4 precautions and usage considerations 4-2
tmpr4955a rev 2.2

chapter 1 introduction 1-1 chapter 1. introduction 1.1 overview the tmpr4955a (to be called ?tx4955a? hereinafter) is a standard microcontroller of 64-bit risc microprocessor tx49 family. the tx4955a uses the tx49/h2 processor core as the cpu. the tx49/h2 processor core is a 64-bit risc cpu core toshiba developed based on the r4000 architecture of mips technologies, inc (?mips?). in addition to its tx49/h2 core with floating point unit (?fpu?), the tx4955a also incorporates peripheral circuits such as sysad bus interface. r4000 is a trademark of mips technologies, inc. 1.2 notation used in this manual 1.2.1 numerical notation ? hexadecimal numbers in this manual are expressed as follows:0x2a (example shown for decimal number 42) ? kb (kilobyte) 2 10 = 1,024 bytes mb (megabyte) 2 20 = 1,024 1,024 = 1,048,576 byte gb (gigabyte) 2 30 = 1,024 1,024 1,024 = 1,073,741,824 bytes 1.2.2 data notation ? byte: eight bits ? half word: two contiguous bytes (16 bits) ? word: four contiguous bytes (32 bits) ? double word: eight contiguous bytes (64 bits) 1.2.3 signal notation ? active-low signals are indicated by adding an asterisk( * ) at the end of the signal name (example: reset * ) ? when a signal is driven to the active voltage level, the signal is said to be ?asserted.? when the signal is driven to an inactive voltage level, it is said to be ?deasserted.? 1.2.4 register notation ? the following nomenclature is used for access attributes. r: r: r: r: read only. cannot be written. w: w: w: w: write only. the bit value is undefined if read. r/w: r/w: r/w: r/w: read/write
chapter 1 introduction 1-2
? c chapter 2 features 2-1 chapter 2. features ? tx49/h2 processor core tx49/h2 processor core tx49/h2 processor core tx49/h2 processor core tx49/h2 processor core is a 64-bit risc cpu core toshiba developed based on the architecture of mips for interactive consumer applications including printer, network and set-top terminals. ? ieee754 compatible single and double precision fpu ieee754 compatible single and double precision fpu ieee754 compatible single and double precision fpu ieee754 compatible single and double precision fpu the floating-point operations fully conform to the requirements of ansi/ieee standard 754-1985, ieee standard for binary floating-point arithmetic. as 32 general purpose register (32 fgrs), each of which is 64 bits wide and 2 control of fpu registers (2 fcrs), each of which is 32bit wide. all floating-point instructions, as defined in the mips isa for the floating-point coprocessor, cp1, are processed by the other hardware unit that executes integer instruction. ? internal bus internal bus internal bus internal bus width width width width i i i is s s s 64-bit, external bus width is 32-bit 64-bit, external bus width is 32-bit 64-bit, external bus width is 32-bit 64-bit, external bus width is 32-bit core and cache are connect with 64-bit internal bus. external bus is sysad-bus i/f. this interface is compatible with the tx4300, r4000, and r5000 system interfaces. ? power management power management power management power management internal: 1.5 v i/o: 3.3 v the tx49/h2 processor support power management mode (halt, doze) ? maximum operating frequency maximum operating frequency maximum operating frequency maximum operating frequency the tx49/h2 processor?s maximum operating frequency is 200 mhz. the sysad-bus i/f and tx49/h2 processor?s maximum operating frequency is set by external pin (divmode (1:0)). ex. core?s operating frequency is 167 mhz/200 mhz div mode (1:0) master clock cpu clock 0 41.8 mhz/50 mhz 167 mhz/200 mhz 1 66.7 mhz/80 mhz 167 mhz/200 mhz 2 83.5 mhz/100 mhz 167 mhz/200 mhz 3 55.7 mhz/66.7 mhz 167 mhz/200 mhz ? package package package package tx4955a: 160-pin qfp ? part number part number part number part number tmpr4955af-167 tmpr4955af-200
? c chapter 2 features 2-2 2.1 block diagram figure 2.1.1 tx4955a processor signals 32 bit sysad bus cg synchro- nize interrupt / reset tx49/h2 core sysad interface 32 kb 4-way set instruction cache 32 kb 4-way set data cache write buffer integer unit system control coprocessor (cp0) gpr data path mac pipeline control cp0 registers mmu / tlb exception unit tx4955a jtag interface dsu (ejtag) masterclock floating-point coprocessor ( cp1) fp registers data path cache controller
? c chapter 2 features 2-3 2.2 pin description 2.2.1 tx4955a pin out (160-pin qfp) table 2.2.1 tx4955a pin out 1 vss 41 vss 81 vccint 121 sysad28 2 bufsel1 42 trst * 82 nmi * 122 sysad29 3jtdo 43 rdrdy * 83 extrqst * 123 vccint 4jtdi 44 wrrdy * 84 reset * 124 vss 5jtck 45 validin * 85 coldreset * 125 sysad30 6jtms 46 validout * 86 vccio 126 vccio 7vccio 47 release * 87 endian 127 vss 8 vss 48 vccio 88 vccio 128 sysad31 9sysad4 49 pllreset * 89 vss 129 sysadc2 10 sysad5 50 vccint 90 sysad16 130 vccint 11 vccint 51 tintdis 91 vccint 131 vss 12 vss 52 vss 92 vss 132 sysadc3 13 sysad6 53 syscmd0 93 sysad17 133 vccio 14 vccio 54 syscmd1 94 sysad18 134 vss 15 vss 55 syscmd2 95 vccio 135 sysadc0 16 sysad7 56 syscmd3 96 vss 136 vccint 17 sysad8 57 syscmd4 97 sysad19 137 vss 18 vccint 58 syscmd5 98 vccint 138 sysadc1 19 vss 59 vccio 99 vss 139 sysad0 20 sysad9 60 vss 100 sysad20 140 vccio 21 vccio 61 syscmd6 101 sysad21 141 vss 22 vss 62 syscmd7 102 vccio 142 sysad1 23 sysad10 63 syscmd8 103 vss 143 sysad2 24 sysad11 64 syscmdp 104 sysad22 144 vccint 25 vccint 65 vccint 105 vccint 145 vss 26 vss 66 vss 106 vss 146 sysad3 27 sysad12 67 vccio 107 sysad23 147 pcst8 28 vccio 68 halt/doze 108 sysad24 148 pcst7 29 vss 69 int0 * 109 vccio 149 pcst6 30 sysad13 70 int1 * 110 vss 150 pcst5 31 sysad14 71 int2 * 111 sysad25 151 pcst4 32 vccint 72 int3 * 112 vccint 152 vccio 33 vss 73 int4 * 113 vss 153 vss 34 sysad15 74 int5 * 114 sysad26 154 vccio 35 bufsel1 75 vccio 115 sysad27 155 vsspll 36 pcst3 76 vss 116 vccio 156 pllcap 37 pcst2 77 tpc3 117 mode43 * 157 vccpll 38 pcst1 78 tpc2 118 divmode1 158 vss 39 pcst0 79 tpc1 119 divmode0 159 masterclock 40 vccio 80 dclk 120 vss 160 vccio note: ? * ? means the signal is the low-active.
? c chapter 2 features 2-4 table 2.2.2 system interface pin name i / o function sysad(31:0) i / o system addres/data bus a 32-bit address and data bus for communication between the processor and an external agent. syscmd(8:0) i / o system command/data identifier bus a 9-bit bus for command and data identifier transmission between the processor and an external agent. sysadc(3:0) i / o system command/data check bus a 4-bit bus containing parity check bits for the sysad bus during data cycle. syscmdp i / o reserved for system command/data identifier bus parity for the tx4955a this signal is unused on input and zero on output. validin * i valid input the external agent asserts validln * when it is driving a calid address or data on the sysad bus and valid command or data identifier on the syscmd bus. validout * o valid output the processor asserts validout * when it is driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. extrqst * i external request an external agent asserts extrqst * to request use of the system interface. release * o release interface signals that the system interface needs to submit an external request. wrrdy * i write ready signals that an external agent can now accept a processor write request. rdrdy * i read ready signals that an external agent can now accept a processor read request. table 2.2.3 clock/control interface pin name i / o function masterclock i master clock master clock input that establishes the processor operating frequency. divmode(1:0) i set the operational frequency of the system interface divmode[1:0] masterclock pclock 00 41.8 mhz/50 mhz 167 mhz/200 mhz 01 66.7 mhz/80 mhz 167 mhz/200 mhz 10 83.5 mhz/100 mhz 167 mhz/200 mhz 11 55.7 mhz/66.7 mhz 167 mhz/200 mhz tintdis i timer-interrupt disable input 0 enable timer-interrupt (can not use int 5 * ) 1 disable timer-interrupt (can use int 5 * ) halt/doze o halt/doze mode output this signal output the status of halt or doze mode. this signal indicates that the tx4955a is in the halt or doze mode when this signal is ?h?. pllreset * i pll reset input a signal to halt the pll oscillation or the tx4955a built-in clock generator. 0 pll is halt (no oscillation) 1 pll is enabled. endian i endianess input indicates the initial setting of the endian during a reset. 0 little endian 1 big endian
? c chapter 2 features 2-5 table 2.2.4 interrupt interface pin name i / o function int(5:0) * i interrupt six lines of general-purpose processor interrupt inputs, which are sampled at rising edges of the master clock. note: int(5) * can use when tintdis signal is ?1?. nmi * i nonmaskable interrupt nonmaskable interrupt input, which is sampled at rising edges of the master clock. table 2.2.5 jtag interface pin name i / o function jtdi i jtag data input / debug interrupt input run-time mode: input serial data to jtag data/instruction registers. real-time mode: interrupt input to change the debug unit state from real-time mode to run-time mode. jtck i jtag clock input clock input for jtag. the jtdi and jtms data are latched on rising edges of this clock. jtdo/tpc(0) o jtag data output / trace pc output data is serially shifted out from this pin. / outputs a non-sequential program counter value synchronously with dclk. jtms i jtag command controls mainly the status transition of the tap controller state machine. when the serial input data is a jtag command, apply a high signal (= 1) to this pin. dclk o debug clock (1/3 cpu clock) clock output for a real-time debug system. timings of the serial monitor bus and pc trace interface signals all are defined by this debug clock dclk. the tx4955a?s operating clock frequency is 1/3 that of pclock. (pclock is internal cpu clock) pcst(8:0) o pc trace status outputs pc trace status information and serial monitor bus mode. tpc(3:1) note 1 o trace pc output outputs a non-sequential program counter value synchronously with dclk. trst * i test reset input reset input for a real-time debug system. when trst * is asserted (= 0), the debug support unit (dsu) is initialized. trst * should be asserted when dsu is not used. note1: leave tpc (3-1) pins open when not using them as pc trace outputs for debugging.
? c chapter 2 features 2-6 table 2.2.6 initialization interface pin name i / o function reset * i reset assert this signal for all reset sequences. also, make sure it is applied synchronously with the master clock. coldreset * i cold reset assert this signal at power-on and for a cold reset. sclock starts operating synchronously with this signal. mode43 * i sysad bus protocol selection the high or low level of this input signal at power-on or cold reset selects the sysad bus protocol. low level: tx4300 type protocol high level: r5000 type protocol bufsel(1:0) i output buffer select select the output buffer type of data bus and control signals. bufsel[1:0] buffer output rate 00 50 % 01 reserved 10 150 % 11 100 % (same as tx4955) pllcap i pll adjusting capacitor reserved table 2.2.7 power supply pin name i / o function vccpll this is a static vcc for the internal phase locked loop. (apply a 1.5 v power supply.) vsspll this is a static vss for the internal phase locked loop. v this is a 3.3 v power supply pin. v this is a 1.5 v power supply pin. vss this is the ground pin.
chapter 3 initialization interface 3-1 chapter 3. initialization interface this chapter describes the tx4955a initialization interface, and the processor modes. this includes the reset signal description and types, and initialization sequence, with signals and timing dependencies, and the user-selectable tx4955a processor modes. signal names are listed in bold letters?for instance the signal masterclock masterclock masterclock masterclock indicates the processor clock. low-active signals are indicated by a trailing asterisk, such as coldreset coldreset coldreset coldreset * , the power-on/cold reset signal. 3.1 functional overview the tx4955a processor has the following two types of resets; they use the coldreset coldreset coldreset coldreset * and reset reset reset reset * input signals. ? cold reset cold reset cold reset cold reset is asserted after the power supply is stable and then restarts all clocks. a cold reset completely reinitializes the internal state machine of the processor without saving any state information. ? warm reset warm reset warm reset warm reset restarts processor, but does not affect clocks. a warm reset preserves the processor internal state. after reset, the processor is bus master and drives the sysad bus. for reset vector address, use oxbfc0 0000. in the tx49/h2 processor core, the reset vector is located in address space without caching. therefore, the cache and tlb need not be initialized at reset processing. 3.1.1 system coordination care must be taken to coordinate system reset with other system elements. in general, bus errors immediately before, during, or after a reset may result in unpredicted behavior. also, a small amount of processor state is guaranteed as stable after a reset of the tx4955a processor, so extreme care must be taken to correctly initialize the processor through software. the operation of each type of reset is described in sections that follow. refer to figure 3.2.1 and figure 3.2.2 later in this chapter for timing diagrams of the cold and warm resets.
chapter 3 initialization interface 3-2 3.2 reset signal description this section describes the two reset signals, coldreset coldreset coldreset coldreset * and reset reset reset reset * . ? coldreset coldreset coldreset coldreset * : the coldreset coldreset coldreset coldreset * signal must be asserted (note) (low) to reset the processor. internal clock begins to cycle and is synchronized with the deasserted edge (high) of coldreset coldreset coldreset coldreset * . coldreset coldreset coldreset coldreset * can be asserted and deasserted asynchronously with the rising edge of masterclock masterclock masterclock masterclock. ? reset reset reset reset * : the reset reset reset reset * signal is asserted synchronously to initiate a warm reset. the reset reset reset reset * signal must be deasserted synchronously with masterclock masterclock masterclock masterclock. note: asserted means the signal is true, or in its valid state. for example, the low-active reset * signal is said to be asserted when it is in a low (true) state. 3.2.1 cold reset a cold reset is used to completely reset the processor, including processor clocks. information about saving processor states is given below. once power to the processor is established, the coldreset coldreset coldreset coldreset * signal is asserted for 64,000 masterclock masterclock masterclock masterclock cycles to ensure time for the processor clocks to lock to the input masterclock masterclock masterclock masterclock. coldreset coldreset coldreset coldreset * can be asserted and deasserted asynchronously with the rising edge of masterclock masterclock masterclock masterclock. reset reset reset reset * can be asserted/deasserted when coldreset coldreset coldreset coldreset * is asserted, but its value must not be changed during the reset sequence. upon reset, the processor becomes bus master and drives the sysad sysad sysad sysad bus. after reset reset reset reset * is deasserted, the processor branches to the reset exception vector and begins executing the reset exception code. for information on the bit states during a cold reset, see the section on cold reset exceptions in cpu exception processing. 3.2.2 warm reset a warm reset is used to reset the processor without affecting the clocks; in other words, a warm reset is a logic reset. asserting the reset reset reset reset * signal resets the processor without disrupting the clocks and allows the processor to retain as much of its state as possible for debugging. (for information on saving the processor states, see the section on soft reset exception in cpu exception processing.) because asserting the reset reset reset reset * signal results in an immediate warm reset, multicycle instructions such as cache misses or floating-point instructions may be aborted and some data lost as a result. a warm reset is started by assertion of the reset reset reset reset * pin. reset reset reset reset * must be asserted for a minimum of 16 cycles, and must be asserted and deasserted synchronously with masterclock masterclock masterclock masterclock. in general, data in the processor is preserved for debugging purposes. upon reset, the processor becomes bus master and drives the sysad sysad sysad sysad bus. after reset reset reset reset * is deasserted, the processor branches to the reset exception vector and begins executing the reset exception code. if reset reset reset reset * is asserted in the middle of a sysad sysad sysad sysad transaction, care must be taken to reset all external agents to avoid sysad sysad sysad sysad bus contention. figure 3.2.1 and figure 3.2.2 show the timing diagrams for the cold and warm resets.
chapter 3 initialization interface 3-3 figure 3.2.1 cold reset figure 3.2.2 warm reset note: as for the pllreset * , there is not need to take the same period with master clock. figure 3.2.3 power on reset v cc masterclock (mclk) coldreset * reset * wavy lines indicate one or more identical cycles, not shown due to space constraints 64,000mclk cycles tdh tds 16mclk cycles v cc masterclock (mclk) coldreset * reset * wavy lines indicate one or more identical cycles, not shown due to space constraints 16mclk cycles tds tdh v cc io v cc int masterclock (mclk) wavy lines indicate one or more identical cycles, not shown due to space constraints coldreset * 64,000mclk cycles 16mclk cycles pllreset * reset * 100 ms internal clock
chapter 3 initialization interface 3-4 3.3 tx4955a the tx4955a processor supports several user-selectable modes. all modes except divmode divmode divmode divmode ratios are set/reset by writing to the status and config registers. 3.3.1 power modes (doze/halt mode) the tx4955a supports three power modes: normal operation, doze, and halt. this section describes these three modes. in tx4955a, there is a terminal showing that the status is halt mode or doze mode state. figure 3.3.1 show the status shifts in the operation mode. figure 3.3.1 status shift among normal operation mode and low power consumption modes ? normal operation mode normally the tx4955a processor clock (pclock pclock pclock pclock) operates at a multiple of the masterclock masterclock masterclock masterclock speed (as designated by the divmode divmode divmode divmode setting). the system interface clock (sclock sclock sclock sclock) operates at the same frequency as masterclock masterclock masterclock masterclock. ? doze mode the user can specify doze mode by setting the halt bit in the config register to 1 after excuting a wait instruction. consumption power is bigger than later halt mode so that a circuit maintaining pipeline status works in doze mode. to recover from doze mode, assert one of the following signal: int[5:0] * , nmi * , reset * , or coldreset * . when recovering from doze mode by asserting a non-enabled int[5:0] * signal, the value of the int mask field in the status register is not affected. when recovering from doze mode via the coldreset * signal, nmi * signal, or an enabled int[5:0] * signal, the top instruction of the exception handler corresponding to the signal is executed. on execution of the top instruction, the epc points to instruction following the wait instruction. when recovering via a non-enabled int[5:0] * signal, the processor resumes execution from the instruction following the instruction used to change to doze mode. ? halt mode the user can change to halt mode by setting the halt bit in the config resister to 0 after excuting a wait instruction. in halt mode, operations are suspended with the pipeline state retained. even requests for bus mastership are ignored. when an instruction that clears the halt bit = 0 and wait inst. halt bit = 1 and wait inst. halt mode doze mode normal operation mode interrupt or reset interrupt or reset interrupt or reset
chapter 3 initialization interface 3-5 wait instruction is executed during a bus operation, the halt mode is after the bus operation completes. write buffer operations do not stop during halt mode: when the write buffer contain date, write operations continue until the write buffer empties. to recover from halt mode, assert one of the following signal: int[5:0] * , nmi * , reset * , or coldreset * . when recovering from halt mode by asserting a non-enabled int[5:0] * signal, the value of the int mask field in the status register is not affected. when recovering from halt mode via the coldreset * signal, nmi * signal, or an enabled int[5:0] * signal, the top instruction of the exception handler corresponding to the signal is executed. on execution of the top instruction, the epc points to instruction following the wait instruction. when recovering via a non-enabled int[5:0] * signal, the processor resumes execution from the instruction following the instruction used to change to halt mode. 3.3.2 operating modes the tx4955a has three operating modes, user mode, supervisor mode and kernel mode, that function in both 32- and 64-bit operations. the ksu, exl and erl bits in the status register select user, supervisor or kernel mode. the ux, sx and kx bits in the status register select 32-bit or 64-bit addressing for user, kernel and supervisor operating modes. ksu exl erl ux sx kx mode 10 0 0 0 ? ? 32-bit addressing for user mode 10 0 0 1 ? ? 64-bit addressing for user mode 01 0 0 ? 0 ? 32-bit addressing for supervisor mode 01 0 0 ? 1 ? 64-bit addressing for supervisor mode 00 ? ? ? ? 0 32-bit addressing for kernel mode ? 1 ? ? ? 0 32-bit addressing for kernel mode ? ? 1 ? ? 0 32-bit addressing for kernel mode 00 ? ? ? ? 1 64-bit addressing for kernel mode ? 1 ? ? ? 1 64-bit addressing for kernel mode ? ? 1 ? ? 1 64-bit addressing for kernel mode 3.3.3 system endianness by setting the external pin (endian), the state of system endianness is provide to the processor. indicateds the initial setting of the endian during a reset. endian = 0: little endian endian = 1: big endian note: be bit in the config register is read only.
chapter 3 initialization interface 3-6 3.3.4 reverse endianness when the re bit in the status register is set, endianess as seen by user software is reversed from its previous state. 3.3.5 instruction trace support consists of an enhanced jtag module and a debug support unit (dsu). it can be used to provide single-step execution and hardware break-points for debugging processor system. ejtag utilizes jtag interface and extends the ability to access the inside register contents, host system peripherals, and system memory. 3.3.6 bootstrap exception vector this bit is used when diagnostic tests cause exceptions to occur prior to verifying proper operation of the cache and main memory system. when set, the bootstrap exception vector ( bev ) bit in the status register causes the tlb refill exception vector to be relocated to a virtual address of 0xffff ffff bfc0 0200 and the general exception vector relocated to address 0xffff ffff bfc0 0380. when bev is cleared, these vectors are located at 0xffff ffff 8000 0000 (tlb refill) and 0xffff ffff 8000 0180 (general). 3.3.7 interrupt enable when ie bit is clear, interrupts are not allowed, with the exception of reset and the nonmaskable interrupt. 3.3.8 floating-point reigsters by setting the fr bit in the status register, the user accesses the full set of 32, 64-bit floating point registers as defined in the mips iii isa. when reset, the processor accesses the registers as defined in the mips ii architecture.
chapter 4 clock interface 4-1 chapter 4. clock interface this chapter describes the clock signals (?clocks?) used in the tx4955a processor. the subject matter includes basic system clocks, system timing parameters, operating the tx4955a processor in reduced power (rp) mode, connecting clocks to a phase-locked system, and connecting clocks to a system without phase locking. 4.1 signal terminology the following terminology is used in this chapter (and book) when describing signals: ? rising edge indicates a low-to-high transition. ? falling edge indicates a high-to-low transition. ? clock-to-q delay is the amount of time it takes for a signal to move from the input of a device ( clock ) to the output of the device ( q ). figure 4.1.1 and figure 4.1.2 illustrate these terms. figure 4.1.1 signal transitions figure 4.1.2 clock-to-q delay single clock cycle high-to-low transition 1234 low-to-high transition clock-to-q delay q data in data out clock in data in data out clock-to-q clock in
chapter 4 clock interface 4-2 4.2 basic system clocks the various clock signals used in the tx4955a processor are described below, starting with masterclock masterclock masterclock masterclock, upon which the processor bases all internal and external clocking. the clocks on the tx4955a processor are controlled by an on-processor phase-locked loop (pll) circuit. this circuit keeps the tx4955a processor?s internal clock edges aligned with the clock edges of the masterclock masterclock masterclock masterclock signal, which itself acts as the master system clock. inside the tx4955a processor, the masterclock masterclock masterclock masterclock signal can be multiplied by a factor set by the divmode (1:0) divmode (1:0) divmode (1:0) divmode (1:0) inputs to the processor. all internal clocks are then derived from this clock. the tx4955a processor has two primary internal clocks, the pipeline (also referred to as processor ) clock, pclock pclock pclock pclock, and the system interface clock, sclock sclock sclock sclock. sclock sclock sclock sclock has the same frequency and phase as masterclock masterclock masterclock masterclock. 4.2.1 masterclock the processor bases all internal and external clocking on the single masterclock masterclock masterclock masterclock input signal. masterclock masterclock masterclock masterclock specifications are shown in figure 4.2.1. t mcf t mcr t mch t mcl t mcp 0.8v cc io 0.2v cc io figure 4.2.1 masterclock 4.2.2 pclock the pipeline (or processor ) clock, pclock pclock pclock pclock, can be 2, 2.5, 3 or 4 times the masterclock masterclock masterclock masterclock frequency. this multiplication factor is determined by divmode (1:0) divmode (1:0) divmode (1:0) divmode (1:0) pins, which are static signal inputs to tx4955a. all internal registers and latches use pclock pclock pclock pclock. 4.2.3 sclock the system interface clock, sclock sclock sclock sclock, is the same as the masterclock masterclock masterclock masterclock frequency. sclock sclock sclock sclock is always derived from pclock. pclock. pclock. pclock. the tx4955a processor drives its outputs on this clock edge. the first rising edge of sclock sclock sclock sclock, after coldreset coldreset coldreset coldreset * is deasserted, is aligned with the first rising edge of masterclock masterclock masterclock masterclock.
chapter 4 clock interface 4-3 4.2.4 pclock-to-sclock division figure 4.2.2 shows the clocks for a pclock-to-sclock division by 2. sysadin sysad driven sclock pclock syncout masterclock cycle t ds t dh t do d d d d d d d d 4 3 12 figure 4.2.2 processor clock, pclock-to-sclock divisor of 2 4.2.5 phase-locked loop (pll) the tx4955a clocks are controlled by a phase-locked loop circuit (pll).
chapter 4 clock interface 4-4 4.3 connecting clocks to a phase-locked system when the processor is used in a phase-locked system, the external agent must phase lock its operation to a common masterclock masterclock masterclock masterclock. in such a system, the delivery of data and data sampling have common characteristics, even if the components have different delay values. for example, transmission time (the amount of time a signal takes to move from one component to another along a trace on the board) between any two components a and b of a phase-locked system can be calculated from the following equation: transmission time = (sclock period) ? (t do for a) ? (t ds for b) ? (clock jitter for a max) ? (clock jitter for b max) figure 4.3.1 shows a block-level diagram of a phase-locked system using the tx4955a processor. masterclock external agent tx4955a masterclock syscmd sysad sysad masterclock syscmd figure 4.3.1 the tx4955a processor phase-locked system
chapter 5 cache organization 5-1 chapter 5 cache organization this chapter describes in detail the cache memory: its place in the tx4955a memory organization, and individual organization of the caches. this chapter uses the following terminology: ? the data cache may also be referred to as the d-cache. ? the instruction cache may also be referred to as the i-cache. these terms are used interchangeably throughout this book. 5.1 memory organization figure 5.1.1 shows the tx4955a system memory hierarchy. in the logical memory hierarchy, both primary and secondary caches lie between the cpu and main memory. they are designed to make the speedup of memory accesses transparent to the user. each functional block in figure 5.1.1 has the capacity to hold more data than the block above it. for instance, physical main memory has a larger capacity than the caches. at the same time, each functional block takes longer to access than any block above it. for instance, it takes longer to access data in main memory than in the cpu on-chip registers. tx49 cpu cpu core core i-cache d-cache caches cache increasing data capacity faster access time memory peripherals main memory disk, cd-rom, tape, etc. figure 5.1.1 logical hierarchy of memory the tx4955a processor has two on-chip caches: one holds instructions (the instruction cache), the other holds data (the data cache). the instruction and data caches can be read in one pclock pclock pclock pclock cycle. data writes are pipelined and can complete at a rate of one per pclock pclock pclock pclock cycle. in the first stage of the cycle, the store address is translated and the tag is checked; in the second stage, the data is written into the data ram.
chapter 5 cache organization 5-2 5.2 cache organization this section describes the organization of the on-chip data and instruction caches. figure 5.2.1 provides a block diagram of the tx4955a cache and memory model. main memory cache controller i-cache: instruction cache d-cache: data cache d-cache i-cache caches tx4955a figure 5.2.1 tx4955a cache support 5.2.1 cache sizes the tx4955a instruction cache is 32 kbytes; the data cache is 32 kbytes. 5.2.2 cache line lengths a cache line is the smallest unit of information that can be fetched from main memory for the cache, and that is represented by a single tag. (note) the line size for the instruction cache is 8 words (32 bytes) and the line size for the data cache is 8 words (32 bytes). note: cache tags are described in the following sections. 5.2.3 organization of the instruction cache (i-cache) each line of i-cache data (although it is actually an instruction, it is referred to as data to distinguish it from its tag) has an associated 24-bit tag. the tx4955a processor i-cache has the following characteristics: ? cache size: 32 kb ? four-way set associative ? fifo replacement ? indexed with a virtual address ? checked with a physical tag ? block (line) size: 8 words (32 bytes) ? burst refill size: 8 words (32 bytes) ? lockable on a per-line basis (way1 way3) ? all valid bits, lock and fifo bits are cleared by a reset exception
chapter 5 cache organization 5-3 5.2.4 instruction cache address field figure 5.2.2 shows the instruction cache address field. when 4-kb page size is in 32 kb i-cache, the bit 12 of the physical address and the virtual address must be same value. cache tag index (8 bits) 35 12 5 4 3 2 0 physical tag (24 bits ) word (2 bits) 11 byte (3 bits) figure 5.2.2 instruction cache address field 5.2.5 instruction cache configuration each line in the 4 ways of the instruction cache share f1, f0 replacement bits. figure 5.2.3 shows the format of replacement bits. these bits are shared by way0, way1, way2 and way3 for 32 kb cache, and indicate next set to which replacement will be directed; when lock bit is set to 1, indicate this set is not locked. each line of instruction cache data has an associated 26-bit tag that contains a 24-bit physical address, a single lock bit and a single valid bit, except for the line in way0, which has an 25-bit tag that excludes a lock bit. figure 5.2.4 shows the formats of tag and data pair. f0: fifo replace bit 0 f1: fifo replace bit 1 10 f1 f2 figure 5.2.3 format of replacement bits 25 0 24 23 0 63 0 63 0 63 0 63 format for way0 0 24 23 0 63 0 63 0 63 0 63 format for way1, 2 and 3 v p tag data data data data v p tag data data data data l l: lock bit (1: enable, 0: disable) v: valid bit (1: valid, 0: invalid) ptag: physical tag (bit 35 12 of the physical address) data: instruction cache data figure 5.2.4 format of tag and data pair for i-cache
chapter 5 cache organization 5-4 5.2.6 organization of the data cache (d-cache) each line of d-cache data has an associated 24-bit tag. the tx4955a processor d-cache has the following characteristics: ? cache size: 32 kb ? four-way set associative ? fifo replacement ? indexed with a virtual address ? checked with a physical tag ? block (line) size: 8 words (32 bytes) ? burst size: 8 words (32 bytes) ? store buffer ? lockable on a per-line basis (way1 way3) ? write-back or write-through on a per-page basis ? all write-back, cs, fifo and lock bits are cleared by a reset exception 5.2.7 data cache address field figure 5.2.5 shows the data cache address field. y when 4-kb page size is used in 32kb d-cache, the bit 12 of the physical address and the virtual address must be same value. cache tag index (8 bits) 35 12 5 4 3 2 0 physical tag (24 bits ) word (2 bits) 11 byte (3 bits) figure 5.2.5 data cache address field 5.2.8 data cache configuration each line in the 4 ways of the data cache share f1, f0 replacement bits. figure 5.2.6 shows the format of replacement bits. these bits are shared by way0, way1, way2 and way3 for 32 kb cache, and indicate next set to which replacement will be directed; when lock bit is set to 1, indicate this set is not locked. each line of data cache data has an associated 28-bit tag that contains a 24-bit physical address, a single lock bit, a single write-back bit and a 2-bit cache state, except for the line in way0, which has an 27-bit tag that excludes a lock bit. figure 5.2.7 shows the formats of tag and data pair. f0: fifo replace bit 0 f1: fifo replace bit 1 10 f1 f2 figure 5.2.6 format of replacement bits
chapter 5 cache organization 5-5 l: lock bit (1: enable, 0: disable) w: write-back bit (set if cache line has written) cs: primary cache state (0: invalid, 1: reserved, 2: reserved, 3: valid) ptag: physical tag (bit 35~12 of the physical address) data: data cache data 23 25 26 0 24 23 63 format for way0 00 63 0 63 63 0 25 26 27 0 24 63 format for way1, 2 and 3 00 63 0 63 63 0 w cs ptag data data data data w cs ptag data data data data l figure 5.2.7 format of tag and data pair for d-cache in the tx4955a, the w (write-back) bit, not the cache state, indicates when the primary cache contents modified data that must be written back to memory. the states invalid and dirty exclusive are used to describe the cache line. that is, there is no hardware support for cache coherency. 5.3 lock function the lock function can be used to locate critical instruction/data in one instruction/data cache set and they are not replaced when the lock bit is set. 5.3.1 lock function setting the lock bit in each line cache enable the instruction/data cache lock function. when the lock function is enabled, the instruction/data in the valid line is locked and never be replaced. the set to be locked is pointed by fifo bit. refilled instruction/data during the lock function is enabled is locked. when a store miss occurs for the write-through data cache without write allocate, the store data is not written to the cache and will therefore not be locked. the lock function is disabled by clearing the lock bit in each line. in order to clear or set the lock bit in the cache, cache instructions (index store i-cache /d-cache tag) can be used, and in order to load the instruction/data to cache from memory, another cache instructions (fill i-cache/d-cache) can be used (refer to cache instruction). clear the lock bit as follows when data written to a locked line should be stored in main memory. (1) read the locked data from cache memory (2) clear the lock bit (3) store the data that was read
chapter 5 cache organization 5-6 5.3.2 operation during lock after the lock bit is set for a line, the line can be replaced only when it?s line state is invalid. the locked valid line can never be replaced. fifo bit should point only to the set of locked invalid line or unlocked line. a write access to a locked valid line takes place only to the cache not to the memory at write back mode. both of the cache and the memory are replaced at write through mode. 5.3.3 example of data cache locking during the load operation to the locked line of the cache, any interrupt should be disabled in order to avoid to lock the wrong data. to lock data cache lines, the following sequence of codes could be used. ....................... / * disable the interrupt * / mtc0 t0, taglo / * load data into taglo reg * / cache 2 (d), offset (base) / * invalidate and lock line in desired set using index_store_tag cache instruction * / cache 7 (d), offset (base) / * fill the cache line from desired memory location * / ....................... / * enable the interrupt * / 5.3.4 example of instruction cache locking to lock instruction cache lines, the following sequence of codes could be used: ....................... / * disable the interrupt * / mtc0 t0, taglo / * load data into taglo reg * / cache 2 (i), offset (base) / * invalidate and lock line in desired set using index_store_tag cache instruction * / cache 5 (i), offset (base) / * fill the cache line from desired memory location * / ....................... / * enable the interrupt * /
chapter 5 cache organization 5-7 5.4 the primary cache accessing figure 5.4.1 shows the virtual address (va) index to the primary cache. each instruction and data cache size is 32 kb. the virtual address bits be used to index into the primary cache decided by the cache size. tags tag line data data line va (12..5) stage wtag va (12..5) 64 figure 5.4.1 primary cache data and tag organization 5.5 cache states the section describes about the state of a cache line. the cache line in the tx4955a are in one of states described in table 5.5.1. the i-cache line is in one of the following states: ? invalid ? valid the d-cache line is in one of the following states: ? invalid ? valid table 5.5.1 cache states cache line state description invalid a cache line that does not contain valid information must be marked invalid, and cannot be used. a cache line in any other state than invalid is assumed to contain valid information. valid a cache line contains valid information. the cache line may or not be consistent with memory and is owned by the processor (see cache line ownership in this chapter).
chapter 5 cache organization 5-8 5.6 cache line ownership the tx4955a becomes the owner of a cache line after it writes to that cache line (that is, by entering the dirty exclusive), and is responsible for providing the contents of that line on a read request. there can only be one owner for each cache line. 5.7 cache multi-hit operation the tx4955a is not guaranteed the operation for the multi-hit of primary cache. thus, in case of locking the specified program/data in the primary cache, the program/data must be used after locked in the cache by fill instruction. such as the previous description the cache multi hit does not guarantee in the tx4955a, however, if it occurs, the tx4955a will do the operation as follows. ? load: read from the higher way of priority (way0 > way1 > way2 > way3). ? store: write to all way that are multi-hits. 5.8 fifo replacement algorithm the instruction and data caches in the tx4955a use the fifo replacement algorithm. ? usually, cache elements are replaced in this order: way0, way1, way2, way3. ? the fifo[1:0] replacement bits do not point to a locked, valid cache line. ? data is first written to a cache line marked invalid, if any. ? the fifo replacement bits change every time memory data is written to the cache or a cache instruction is executed. figure 5.8.1 shows several examples of how the fifo replacement bits change. a) way0 invalid way1 invalid way2 invalid way3 invalid b) c) d) way0 invalid way1 invalid lock way2 invalid way3 invalid way0 invalid way1 invalid way2 valid way3 invalid way0 invalid way1 valid lock way2 invalid way3 valid e) f) way0 invalid way1 valid lock way2 valid lock way3 valid lock way0 valid way1 valid way2 valid lock way3 valid figure 5.8.1 examples of cache state transitions by the fifo replacement algorithm
chapter 5 cache organization 5-9 5.9 cache testing 5.9.1 cache disabling the ice# and dce# bits in the config register enable and disable the instruction and data caches respectively. when the cache is disabled, any attempt to access the cache causes a cache miss; therefore, a cache refill does not occur. (a burst bus cycle does not occur, either, as is the case with an access to a uncached memory space.) with the cache disabled, the valid (v) and cache state (cs) bits for each entry remain unchanged. note: when the instruction cache is disabled all instruction fetches cause an instruction cache miss. external memory accesses will occur as a single-read operation. instruction cache operations by the cache instruction are valid. note: when the data cache is disabled all memory accesses by the load and store instructions cause a data cache miss. at this time, no cache refill occurs. external memory accesses will occur as a single-read or single-write operation. data cache operations by the cache instruction are valid. note: how to disable the instruction cache reliably to disable the instruction cache, stop instruction streaming by following the mtc0 instruction with a jump instruction, as shown below: example: mtc0 rn, config (set ice# bit.) j l1 (jump to l1 and stop streaming.) nop (jump delay slot) l1: cache indexinvalidate, offset (base) 5.9.2 cache flushing both the instruction and data caches are flushed by a cold reset or warm reset exception. i:e., all the valid and cs bits are cleared to zeroes. the instruction cache is also flushed by the index invalidate and hit invalidate operations with a cache instruction. the data cache is flushed by the hit invalidate operation with a cache instruction. data is written back to the main memory when an index writeback invalidate or hit writeback invalidate operation is performed, when a hit writeback operation is performed, and when a cache line is replaced. when the write-back policy is employed, it is required to consciously maintain cache coherency when flushing the cache.
chapter 5 cache organization 5-10 5.10 cache operations as described earlier, caches provide fast temporary data storage, and they make the speedup of memory accesses transparent to the user. in general, the processor accesses cache-resident instructions or data through the following procedure: 1. the processor, through the on-chip cache controller, attempts to access the next instruction or data in the appropriate cache. 2. the cache controller checks to see if this instruction or data is present in the cache. ? if the instruction/data is present, the processor retrieves it. this is called a cache hit . ? if the instruction/data is not present in the cache, the cache controller must retrieve it from memory. this is called a cache miss . 3. the processor retrieves the instruction/data from the cache and operation continues. it is possible for the same data to be in two places simultaneously: main memory and cache. this data is kept consistent through the use of a write-back methodology; that is, modified data is not written back to memory until the cache line is to be replaced. instruction and data cache line replacement operations are listed in described as the following sections. table 5.10.1 cache instruction name caches operation index invalidate instruction sets the cache state of cache block to invalid. index write back invalidate data examines cache state, if valid dirty, then that block is written back to main memory. then the cache block is set to invalid. index load tag instruction & data read the tag for the cache block at the specified i ndex and place it into taglo. index store tag instruction & data write the tag for the cache block at the specified index from the taglo register. create dirty exclusive data if the cache does not contain the specified address, and the block is valid dirty the block will be written back to main memory. then the tag w ill be set to the specified physical address and will be marked valid. hit invalidate instruction & data if the cache block contains the specified address, cache block will be marked invalid. hit write back invalidate data if the cache block contains the specified address, and it is valid dirty, the data will be written back to main memory. then, the cache block is marked invalid. fill instruction fill the instruction cache block from main memory. fill data fill the data cache block from memory. hit write back data if the cache block contains the specified address, and it is marked valid dirty, the block will be written back to main memory, and marked valid clean.
chapter 5 cache organization 5-11 5.10.1 cache write policy the tx4955a processor manages its data cache by using a write-back and a write-through policy. a write-back stores write data into the cache, instead of writing it directly to memory. some time later this data is independently written into memory. in the tx4955a implementation, a modified cache line is not written back to memory until the cache line is to be replaced either in the course of satisfying a cache miss, or during the execution of a write-back cache instruction. when the processor writes a cache line back to memory, it does not ordinarily retain a copy of the cache line, and the state of the cache line is changed to invalid. a write-through is written simultaneously to cache and memory. 5.10.2 data cache line replacement since the data cache uses a write-back and a write-through methodology, a cache line load is issued to main memory on a load or store miss, as described below. after the data from memory is written to the data cache, the pipeline resumes execution. tx4955a does not support ?critical data word first?. always it transfer the data of first address. rules for replacement on data load and data store misses are given below. ? data load miss data load miss data load miss data load miss if the missed line is not dirty, it is replaced with the requested line. if the missed line is dirty, it is moved to the write buffer. the requested line replaces the missed line, and the data in the write buffer is written to memory. ? data store miss data store miss data store miss data store miss if the missed line is not dirty, the requested line is merged with the store data and written to memory. if the missed line is dirty, it is moved to the write buffer. the requested line is merged with the store data and written to cache, and data in the write buffer is written to memory. the data cache miss penalties, in number of sclock cycles, are given in table 5.10.2. table 5.10.2 data cache refill penalty cycle count number of pclock cycles action 1 stall the dc stage. 1 transfer address to the write buffer and wait for the pipeline start signal 1 2 transfer address to the internal sysad bus on the sclock. 2 transfer to the external sysad bus. m time needed to access memory, measured in pclock cycles. 4 transfer the cache line form memory to the sysad bus. 2 transfer the cache line from the external bus to the internal bus. 0 restart the dc stage.
chapter 5 cache organization 5-12 5.10.3 instruction cache line replacement for an instruction cache miss, refill is done using sequential ordering, starting from the first word of the retrieved cache line. during an instruction cache miss, a memory read is issued. the requested line is returned from memory and written to the instruction cache. at this time the pipeline resumes execution, and the instruction cache is reaccessed. the replacement sequence for an instruction cache miss is: 1. move the instruction physical address to the processor pads. 2. wait for a pclock cycle, aligned with an sclock boundary, to occur. 3. read the line from memory and write it out to the instruction cache array. 4. restart the processor pipe. the instruction cache miss penalties, in number of pclock, is given in table 5.10.3. table 5.10.3 instruction cache refill penalty cycle count number of pclock action 1 stall the rf stage. 1 transfer address to the write buffer and wait for the pipeline start signal. 1 2 transfer to the external sysad bus. 2 transfer to the external sysad bus. m time needsd to access memory, measured in pclock cycles. 8 transfer the cache line from memory to the sysad bus. 2 transfer the cache line from the external bus to the internal bus. 0 restart the rf stage. 5.11 manipulation of the caches by an external agent the tx4955a does not provide any mechanisms for an external agent to examine and manipulate the state and contents of the caches.
chapter 6 tx4955a system interface 6-1 chapter 6. tx4955a system interface 6.1 terminology the following terms are used in this section. ? external agent: logic device that is directly connected to the processor via the system interface so a processor can issue (instructions). ? system event: event issued inside a processor which, when generated, means that access to external system resources is required. ? sequence: strict order of requests that the processor generates in order to provide service for system events. ? protocol: shift of signals for each cycle generated on the system interface so processor requests or external requests can be asserted. ? syntax: strict definition of the bit pattern on the encoded bus (command bus, etc.). 6.2 explanation of system interface of r5000 type protocol mode in tx4955a, it is built in system interface function corresponding to tx4300 type protocol. a selection of above-mentioned r5000 type protocol mode or tx4300 type protocol mode increases by external pin (mode43 * : 117 pin). mode43 * = 0: tx4300 type protocol mode43 * = 1: r5000 type protocol the tx4955a processor supports 32-bit address/data interfaces. this processor makes it possible to construct a processor system by processors and main memory. system interfaces consist of the following components: ? 32-bit address/data bus, sysad ? 4-bit sysad check bus, sysadc ? 9-bit command bus, syscmd ? 1-bit syscmd check parity, syscmdp ? 6 handshake signals ? rdrdy * , wrrdy * ? extrqst * , release * ? validin * , validout * the tx4955a processor accesses external resources using the system interface in order to correct cache misses, uncached operation, and other problems.
chapter 6 tx4955a system interface 6-2 6.2.1 interface bus figure 6.2.1 illustrates the 32-bit address/data bus sysad (31:0), which is the main communication bus of the system interface, and the 9-bit command bus syscmd (8:0). sysad and syscmd are bi-directional busses. in other words, these two busses are used for the processor to issue processor requests and for the external agent to issue external requests. figure 6.2.1 system interface bus requests sent via the system interface consist of the following: ? address ? system interface command that strictly specifies the type of request ? series of data elements for when the request is a particular write or read process. 6.2.2 address cycle and data cycle cycles during which valid addresses exist on the sysad bus are referred to as address cycles. also, cycles during which valid data exist on the sysad bus are referred to as data cycles. validity is determined depending on the validin signals and validout signals. the syscmd bus is used to identify the contents of the sysad bus for all cycles at which it is to be valid. the most significant bit of the syscmd bus is used to indicate whether the current cycle is an address cycle or a data cycle. ? in the case of an address cycle [syscmd(8) = 0], the remaining bits syscmd(7:0) of the syscmd bus contain the system interface commands. ? in the case of a data cycle [syscmd(8) = 1], the remaining bits syscmd(7:0) of the syscmd bus contain the data identifier. syscmd (8:0) sysad (31:0) tx4955a external agent
chapter 6 tx4955a system interface 6-3 6.2.3 issue cycle two types of processor issue cycles exist with the tx4955a. ? processor read request issue cycles. ? processor write request issue cycles. the tx4955a judges the issue cycle of the processor read request by sampling the rdrdy * signal. it also judges the issue cycle of the processor write request by sampling the wrrdy * signal from the external agent. as illustrated in figure 6.2.2, rdrdy * must be asserted two cycles before the processor read request address cycle in order to define the address cycle as an issue cycle. figure 6.2.2 rdrdy * signal status in case of read request as illustrated in figure 6.2.3, wrrdy * is asserted two cycles before the initial address cycle of the processor write request, and the address cycle must be defined as the issue cycle. figure 6.2.3 wrrdy * signal status in case of write request the tx4955a repeats the request address cycle until the conditions of the valid issue cycle are met. if the processor request is a data transmission, then data transmission starts at the point when the issue cycle is complete. there is only one issue cycle no matter what the processor request is. the tx4955a accepts external requests even while trying to issue processor requests. if the external agent asserts extrqst * , the processor responds to the external agent by releasing the system interface and going into the slave state. rules relating to the issue cycle of processor requests are strictly applied in determining the processor run operation as well. the tx4955a performs one of the following: address 1 issue cycle 23456 cycle master clock sysad bus rdrdy * validout * address 1 issue cycle 23456 cycle master clock sysad bus wrrdy * validout * data
chapter 6 tx4955a system interface 6-4 ? complete issuing of processor requests before external requests are received. ? release the system interface and go into the slave mode without completing issuance of the processor requests. in the latter of the above situations, the tx4955a issues processor requests after external requests are complete. rules relating to issuing are also provided to processor requests. 6.2.4 handshake signal the processor uses the eight control signals explained below to manage the flow of requests. ? rdrdy * and wrrdy * are used by the external agent to indicate that it is ready to accept a new read or write transaction. ? extrqst * and release * are used to transfer sysad bus and syscmd bus control. extrqst * is used by the external agent to indicate the necessity of controlling the interface. release * is asserted by the processor when transferring the system interface access privileges. ? the tx4955a processor uses validout * and the external agent validin * signals to indicate the valid command/data on the syscmd/sysad bus. 6.2.5 system interface protocol of r5000 type figure 6.2.4 illustrates the system interface that operates between registers. in other words, processor output is directly transferred from the output register and changes and the master clock rising edge. processor input is directly transferred to the input register and the input register latches these input signals at the rising edge of the master clock. in this way, it becomes possible for the system interface to operate at the fastest clock frequency. figure 6.2.4 operation of the system interface between registers master clock tx4955a output data input data
chapter 6 tx4955a system interface 6-5 6.2.5.1 master state and slave state the system interface is placed in the master state when the tx4955a processor is driving the sysad bus and syscmd bus. in contrast, the system interface is in the slave state when the external agent is driving the sysad bus and syscmd bus. the processor asserts the validout * signal if the sysad bus and syscmd bus become valid when the system interface is in the master state. the external agent asserts the validin * signal if the sysad bus and syscmd bus become valid when the system interface is in the slave state. 6.2.5.2 shifting from the master state to the slave state the system interface remains in the master state unless it enters one of the following states: ? the external agent issues a request, then usage of the system interface is granted (external arbitration). ? the processor issues a read request and shifts into the slave mode by itself. 6.2.5.3 external arbitration the external agent cannot issue external requests via the system interface unless the system interface goes into the slave state. shifts from the master state to the slave state are arbitrated by the processor using the system interface handshake signals extrqst * and release. * this shift is performed as follows below. 1) the external agent sends notification that it would like to issue an external request by asserting the extrqst * signal. 2) the processor releases the system interface and changes its state from the master state to the slave state by asserting the release * signal for 1 cycle. 3) the system interface returns to the master state when issuing of the external request is complete. 6.2.5.4 shifting to the slave state on its own shifting to the slave state on its own means that the shift from the master state to the slave state is started by the processor when the processor read request is still on hold. the release signal is automatically asserted after the read transaction. self-invoked shifting to the slave state occurs either during the issue cycle of the read request or several cycles after that. after shifting to the slave state on its own, the processor returns to the master state at the end of the next external request. this is made possible by a read request or other type of external request. the sysad bus and syscmd bus drives must start after the external agent confirms that the processor autonomously shifted to the slave state. while the system interface is in the slave state, the external agent can start making external requests without requesting access to the system interface (without asserting the extrqst * signal). the system interface returns to the master state when the external request ends. if a processor read request is on hold after a read request is issued, the processor automatically changes the system interface into the slave state even if the system interface access necessary for the system agent to issue the external request has not been requested. by shifting to the slave state in this manner, the external agent becomes able to return read response data.
chapter 6 tx4955a system interface 6-6 6.2.6 processor requests and external requests requests are broadly categorized as processor requests and external requests. this section will describe these two categories. when a system event is generated, either a single request or a series of requests (referred to as processor requests) are issued via the system interface so the processor can access an external resource and invoke the service for the event. in order for this operation to be performed properly, the processor system interface must be connected to a system agent that meets the two following conditions: 1) it is in compliance to the system interface protocol. 2) it can regulate access to system resources. an external agent that requests access to the processor cache or the status registers generates an external request. this access request is transferred via the system interface. figure 6.2.5 illustrates the system event and request cycles. figure 6.2.5 requests and system event 6.2.6.1 rules relating to processor requests the following rules apply to processor requests. ? after a processor read request is issued, the processor cannot issue the next read request until after it receives a read response. ? when in the r4000 compatible mode, after a write request is issued, at least 4 cycles must pass from when the write request issue cycle is complete until the processor can issue the next request. this is because two dummy system cycles are inserted as illustrated in figure 6.2.6 by consecutive write requests of single data cycles. figure 6.2.6 timing of consecutive write cycles system events ~? load miss ~? store miss ~? store bit ~? uncached load/store ~ cache o p eration processor request ~? read ~? write processor request ~? read ~? write ~? null tx4955a external agent addr 1 23456 cycle master clock sysad bus wrrdy * validout * addr 78910 data dummy data dummy dummy cycle1234 write #1 write #2
chapter 6 tx4955a system interface 6-7 6.2.6.2 processor requests the term ?processor request? refers to either a single request or a series of requests issued via the system interface in order to access external resources. as illustrated in figure 6.2.7, there are two types of processor request: read and write. figure 6.2.7 processor requests read requests are requests that read data from main memory or other memory resources in block double word, partial double word, word, and partial word units. write requests are requests that write data to main memory or other system resources in block, double word, partial double word, word, and partial word units. processor requests are managed by the tx4955a processor in the same manner as the r4000/r4400 non-secondary cache mode. the processor issues requests strictly according to a sequential method. in other words, the processor cannot issue the next request while a previous request is on hold. for example, after issuing a read request, the processor waits for a read response before issuing the next request. the processor only issues write requests when there are no read requests on hold. when using processor input signals rdrdy * and wrrdy * , the external agent can control the processor request flow. rdrdy * is the signal that controls the processor read flow, and wrrdy * controls the processor write request flow. figure 6.2.8 illustrates the sequence of the processor request cycle. figure 6.2.8 processor requests 6.2.6.3 processor read requests when the processor issues a read request, the external agent must access the specified resource and return the requested data. the external agent returns response data for processor read requests so they can be executed separately from the requests. in other words, the external agent can start an external request before returning response data for the processor read request. a processor read request is complete when the final word of the response data is received from the external agent. depending on the data identifier combined with the response data, an error in the response data may be pointed out. the processor would then treat this error as a bus error. if data have not been returned to the issued processor read request, the applicable request is said to be ?on hold.? this state continues until the requested read data are returned. processor request ~? read ~? write tx4955a external agent 1. processor issues read/ write requests. tx4955a external agent 2. external system controls acceptance of requests by asserting either rdrdy * or wrrdy * .
chapter 6 tx4955a system interface 6-8 the external agent must be able to accept processor read requests at any time if either of the two following conditions is met. ? there is no processor read request that is on hold. ? the rdrdy * signal is asserted for 1 cycle 2 cycles before the issue cycle. 6.2.6.4 processor write request when the processor issues a write request, the specified resources are accessed, then the data are written to those resources. processor write requests are complete when the final data word is transferred to the external agent. the external agent must be able to accept processor write requests at any time if either of the two following conditions are met. ? there is no processor read request that is on hold. ? the wrrdy * signal is asserted for 1 cycle 2 cycles before the issue cycle. 6.2.6.5 external requests as illustrated in figure 6.2.9, there are three types of external request: read, write, and null. this section will explain read responses, which are special external request cases. figure 6.2.9 external requests read requests are used to call 1-word data from processor internal resources. write requests are used to write 1-word data to the processor internal resources. null requests are requests that do not require processor operation. as illustrated in figure 6.2.10, the processor uses arbitration signals extrqst * and release * to control the flow of external requests. the external agent cannot issue external requests unless access privileges to the system interface are obtained. in order to do so, the external agent asserts the extrqst * signal, then waits until the processor asserts the release * signal for 1 cycle. figure 6.2.10 external requests external request ~? read ~? write ~? null tx4955a external agent 1. external system requests bus access privileges by asserting the extrqst * signal tx4955a external agent 2. processor grants access privileges by asserting the release * signal 3. external system issues external request 4. processor obtains bus access privileges again
chapter 6 tx4955a system interface 6-9 after the external request is issued, the system interface access privileges always return to the processor. the processor will not accept another external request until the current one is complete. if there is no processor request that is on hold, the processor decides based on the interior state whether to accept an external request or to issue a new processor request. the processor can issue a new processor request even if the external agent requested access to the system interface. the external agent sends notification that it would like to start an external request by asserting the extrqst * signal. after that, the external agent waits for the processor to assert the release * signal and send notification that preparations have been made to accept this request. the processor sends notification based on the next judgement criterion to be listed that preparations have been made to accept an external request. ? the processor ends processor requests that are in progress. ? the processor can accept an external request while waiting for the rdrdy * signal to be asserted so a processor read request can be issued. however, this request must be transferred to the processor at least 1 cycle before the rdrdy * signal is asserted. ? the processor can accept an external request while waiting for the wrrdy * signal to be asserted so a processor write request can be issued. however, this request must be transferred to the processor at least 1 cycle before the wrrdy * signal is asserted. ? if waiting for a response to a read request after the processor shifted itself to the slave state, the external agent can issue an external request before sending read response data. 6.2.6.6 external read requests in contrast to processor read requests, data are directly returned as a response to the request for external read requests. no other requests can be issued until the processor returns the requested data. external read requests are complete when the processor returns the requested data word. depending on the data identifier combined with the response data, an error in the response data may be pointed out. the processor would process the error as a bus error. note: the tx4955a does not have any resources that can read external read requests. the processor returns to the external read request undefined data and data identifiers in which syscmd(5) of the errant data bit is set. 6.2.6.7 external write requests when the external agent issues a write request, the specified resources are accessed, then the data are written to those resources. external requests are complete when the data word is transferred to the processor. the only processor resource that an external write request can use are the interrupt registers.
chapter 6 tx4955a system interface 6-10 6.2.6.8 read responses as illustrated in figure 6.2.11, read responses return data to processor read requests. read responses are external requests, strictly speaking, but there is only one difference with other external requests: read responses do not request permission to use the system interface. therefore, read responses are handled separately from other external requests and are simply referred to as read responses. figure 6.2.11 read response 6.2.7 handling of requests this section will describe in detail sequences, protocol, and syntax for both processor and external requests. ? load miss ? store miss ? store bit ? cache operation ? load linked/store conditional 6.2.7.1 load miss if a processor load miss occurs in the primary cache, the processor cannot proceed to the next process if the cache line that contains the loaded data elements is not received from the external agent. if the current cache line set in which the write back bit (w bit) is set is replaced by a new cache line, the current cache line must be written back. the processor checks the coherency properties in the tlb entries for pages including the requested cache lines. if the coherency properties are non-coherent, then a non-coherent read request is issued. table 6.2.1 indicates the measures that can be taken when a load miss occurs in the primary cache. table 6.2.1 load miss to the primary cache state of the replaced data cache line page properties dirty (w = 0)/invalid dirty (w = 1) non-coherent ncr ncr/w ncr: processor non-coherent, block read request ncr/w: processor non-coherent, block write requests continue after the block read request 6.2.7.2 store miss when a store miss occurs in the primary cache, the processor cannot proceed to the next process if it does not receive from the external agent a cache line that includes a store target address. the processor checks the coherency properties in the tlb entries for pages including the requested cache line, then confirms whether to invalidate write transactions to that cache line or not. after that, the processor executes one of the following requests: 1. read request tx4955a external agent 2. read response
chapter 6 tx4955a system interface 6-11 ? if the coherency properties are non-coherent write back or non-coherent write through (write allocate), then a non-coherent block read request is issued. ? if the coherency properties are non-coherent write through (non-write allocate), then a non-block write request is issued. table 6.2.2 indicates the measures taken when there is a store miss to the primary cache. table 6.2.2 store miss to primary cache state of the replaced data cache line page properties dirty (w = 0)/invalid dirty (w = 1) non-coherent write back or non-coherent write through (write allocate) ncr ncr/w non-coherent write through (non-write allocate) ncw na ncr: processor non-coherent, block read request ncr/w: processor non-coherent, block write requests continue after the block read request ncw: processor non-coherent write request 6.2.7.3 store hits operation in the system interface is determined by whether a line is write back or write through. when in the primary cache mode, all lines set to write back are set to the dirty exclusion state (w = 1). in other words, burst transactions do not occur even if a store hit occurs. lines set to write through generate processor write requests for store data. 6.2.7.4 uncached load or store when performing uncached load operations, the processor issues non-coherent read requests for double words, partial double words, words, or partial words. also, when performing uncached store operations, the processor issues write requests for double words, partial double words, words, or partial words. the tx4955a judges that there is valid parity and data in the entire 32-bit sysad bus even for data requests of less than words. even if there was a partial word request for example, all parity must be correctly returned for all 32 bits. if not, then parity check must be disabled. all write transactions by the tx4955a are buffered in the 4-stage write buffer of the system interface. if there are entries in the write buffer when a block request is required, the write buffer is flushed before a read request is generated (for cache misses or read transactions to uncached areas). data cache misses or uncached data load transactions flush the write buffer. 6.2.7.5 cache instruction operation various operations are made available to the cache instruction in order to maintain the primary cache status and contents. when cache instruction operations are in progress, write requests or invalidate requests can be issued from the processor.
chapter 6 tx4955a system interface 6-12 6.2.8 processor request and external request protocol this section explains the bus arbitration protocol for both processor requests and external requests on a cycle-by-cycle basis. table 6.2.3 below describes the abbreviations used in the following timing diagram of the bus. table 6.2.3 system interface request range abbreviation meaning total unsd unused addr physical address sysad bus data data number n of the data block cmd undefined system interface command read processor or external read request command write processor or external write request command sinull external null request command that releases the system interface ndata non-coherent data identifier for datum other than the final datum syscmd bus neod non-coherent data identifier for the final datum 6.2.8.1 processor request protocol processor request protocol is as follows. ? read ? write ? null write 6.2.8.2 processor read request protocol the processor read request protocol is as described in the following sequence. the next step numbers correspond to the numbers in figure 6.2.12. 1. rdrdy * is asserted to low by the external agent. this means that the external agent is ready to accept read requests. 2. when the system interface is in the master state, the read command is transmitted to the syscmd bus, then the processor read request is issued by transmitting the read address to the sysad bus. 3. at the same time, the processor asserts the validout * signal for one cycle. this means that valid data are being transmitted to the syscmd bus and sysad bus. 4. the processor goes into the slave state by itself either at the issue cycle of a read request or after the release * signal is asserted for one cycle and the issue cycle of the read request is complete. note: the external agent must not assert the extrqst * signal as a means of returning a read response. it must however wait to shift to the slave state on its own. if an external request other than a read response is issued, extrqst * can be asserted either before the read response or in the process of the read response. 5. the syscmd bus and sysad bus are released from the processor one cycle after the release * signal is asserted. 6. the syscmd bus and sysad bus are driven by the external agent within two cycles after the release * signal is asserted. when shifting to the slave state (from cycle 5 in figure 6.2.12), the external agent can return the requested data as a read response. notification of an error in the
chapter 6 tx4955a system interface 6-13 returned data is sent if either the data requested by a read response were returned or if the requested data could not be fetched. in this case, the processor handles the result as a bus error exception. figure 6.2.12 illustrates a situation in which the slave state is autonomously shifted to after a processor read request is issued. note:the timing of the sysadc bus and syscmdp bus are the same as the timing of the sysad bus and syscmd bus timing, respectively. figure 6.2.12 processor read request protocol if the release * signal is asserted, this means that either there is autonomous shifting to the slave state or there is a response to the extrqst * signal assertion. in this case, the processor can accept either a read response or an external request other than a read response. if an external request other than a read response is issued, the processor asserts release * for 1 cycle, then autonomously shifts to the slave state again after the external request process. 6.2.8.3 processor write request protocols either of the two following protocols is used in issuing processor write requests. ? the word write request protocol (see note below) is used for double word, partial double word, word or partial word writing. note: words are called to differentiate from the block request protocol. it is actually possible to transfer data in double word, partial double word, word, or partial word units. ? the block write request protocol is used for block write transactions. the system interface is used in the master state to issue processor double word write requests. figure 6.2.13 illustrates processor non-coherent single word write request cycles. 1. in order to issue a processor single word write request, a write command is sent to 1 23456 cycle master clock sysad bus validout * validln * 78910 11 12 syscmd bus addr read rdrdy * wrrdy * release * master slave 2 5 6 3 1 4
chapter 6 tx4955a system interface 6-14 the syscmd bus, and a write address is sent to the sysad bus. 2. the processor asserts the validout * signal 3. the processor sends the data identifier to the syscmd bus and transmits data to the sysad bus. 4. the data identifier for this data cycle must receive an indication that this is the final data cycle. validout * is deasserted at the end of the cycle. note: the sysadc bus and syscmd bus timing is the same as the sysad bus and syscmd bus, respectively. figure 6.2.13 processor non-coherent single word write request protocol 1 23456 cycle master clock sysad bus validout * validln * 78910 11 12 syscmd bus addr write rdrdy * wrrdy * release * master 1 2 data 0 neod 3 4
chapter 6 tx4955a system interface 6-15 6.2.8.4 processor single write requests there are three processor single write requests as follow below. with later g2sconfig-regster, these modes are selected. 1. r4000 compatible write 2. reissue write 3. pipeline write table 6.2.4 data transfer rate, data pattern and setting at single write requests maximum data transfer rate data pattern setting bit(2:1) write mode 1 double word/3 master clock cycle dxx 00 r4000 compatible reserved reserved 01 reserved 1 double word/1 master clock cycles d 10 pipeline write 1 double word/1 master clock cycles d 11 reissue write note: the setting bit(2:1) is bit(2:1) of the g2sconfig register (0xf ff10 0000). bit(2:1) is set to ?00? when initialized. 1. r4000 compatible write when in the r4000 compatible write mode, 4 cycles are required for single write operation. after the address is asserted for 1 cycle, it is followed by 2 cycles of dummy data. figure 6.2.14 illustrates its basic operation. in the case of the tx4955a, the wrrdy * signal must be asserted for 1 cycle 2 cycles before the write operation is issued. when in the r4000 compatible signal write mode, the external agent receives the write data then immediately asserts wrrdy * , making it possible to stop write operation that continues after 4 cycles. the 2 cycles of dummy data that follow these write data give the external agent time to stop the next write operation. figure 6.2.14 r4000 compatible write 1 23456 cycle master clock sysad bus validout * validln * 78910 11 12 syscmd bus addr rdrdy * wrrdy * release * data 0 addr data 1 addr write neod write neod write
chapter 6 tx4955a system interface 6-16 2. reissue write when in the reissue write mode, the wrrdy * signal is asserted for 1 cycle 2 cycles before the address cycle, and the write operation is reissued when the wrrdy * signal is asserted during the address cycle. figure 6.2.15 illustrates the reissue write protocol. ? by asserting (low) the wrrdy * signal in the first and third cycles, addr0/data0 issues a write operation in the third or fourth cycle. ? by deasserting (high) the wrrdy * signal in the fifth cycle, addr1/data1 does not issue a write operation in the fifth and sixth cycles. ? by asserting (low) the wrrdy * signal again in the eighth and tenth cycles, addr1/data issues a write operation in the tenth and eleventh cycles. figure 6.2.15 reissue write protocol 3. pipeline write similar to when in the r4000 compatible write mode, the pipeline write protocol issues a write operation if the wrrdy * signal is asserted for 1 cycle 2 cycles before the write operation is issued. however, the 2 cycles of dummy data after the write operation are deleted. the external agent must be able to accept one write operation or more after wrrdy * is deasserted. figure 6.2.16 illustrates this protocol. ? third, fourth cycle addr0/data0 is issued by asserting (low) the wrrdy * signal in the first cycle. ? fifth, sixth cycle addr1/data1 is issued by asserting (low) the wrrdy * signal in the third cycle. ? addr2 is not issued in the seventh cycle when the wrrdy * signal is deasserted (high) in the fifth cycle. addr2/data2 is issued in the tenth, eleventh cycle by asserting the wrrdy * signal again in the eighth cycle. figure 6.2.16 pipeline write protocol 1 23456 cycle master clock sysad bus wrrdy * 78910 11 12 syscmd bus addr0 issue data0 addr1 data1 data 1 write neod write neod neod no issue no issue no issue no issue issue addr1 write 1 23456 cycle master clock sysad bus wrrdy * 78910 11 12 syscmd bus addr0 issue data0 addr1 data1 data 1 write neod write neod neod no issue no issue no issue issue addr2 write issue
chapter 6 tx4955a system interface 6-17 6.2.8.5 processor block write request the master state system interface is used to issue processor block write requests. figure 6.2.17 illustrates a processor non-coherent block request made for 8-word data with the ?d? data pattern. 1. processor sends a write command to the syscmd bus, then sends a write address to the sysad bus. 2. processor asserts the validout * signal. 3. processor sends data identifier to the syscmd bus and sends data to the sysad bus. 4. processor asserts the validout * signal only for the number of cycles required to transfer the data block. 5. final data cycle directive must be included in data identifiers for the final data cycle. note: there is transmission protocol of processor block write request three kinds same as processor single write requests. with later g2sconfig-regster, these modes are selected. figure 6.2.17 processor non-coherent block request protocol 6.2.8.6 external request protocol external requests can only be issued when the system interface is in the slave state. the external agent asserts the extrqst * signal, and requests use of the system interface. the processor asserts the release * signal, releases the system interface, waits for it to enter the slave state, then the external agent issues an external request. if the system interface is already in the slave mode, namely, if the processor has put the system interface in the slave state on its own, then the external agent can immediately issue an external request. in the case of the external agent, the system interface must be returned to the master state after issuing an external request. when the external agent issues a single external request, extrqst * must be deasserted 2 cycles after the cycle at which release * is asserted. also, when issuing a series of external requests, the extrqst * signal must be asserted before the last request cycle. master clock data5 1 23456 cycle sysad bus validout * validln * 78910 11 12 syscmd bus addr write rdrdy * wrrdy * release * master 1 4 3 data0 ndata data1 ndata data2 ndata data3 ndata 2 data4 data6 data7 ndata ndata ndata neod 5
chapter 6 tx4955a system interface 6-18 the processor continues processing external requests while extrqst * is asserted. however, until the processor completes a request that is currently being processed, it will not be able to release the system interface and put it into the slave state in preparation for the next external request. also, until extrqst * is asserted, a series of external requests cannot be interrupted by a processor request. 6.2.8.7 external arbitration protocol as previously mentioned, the extrqst * signal and release * signal are used in system interface arbitration. figure 6.2.18 illustrates the timing of the arbitration protocol when the slave state changes to the master state. the arbitration cycle sequence is as follows. 1. the external agent asserts extrqst * when it becomes necessary to issue external requests. 2. the processor asserts release * for 1 cycle when it becomes possible to process an external request. 3. the processor sets the sysad bus and syscmd bus to tri-state. 4. the external agent must start transmission to the sysad bus and syscmd bus 2 cycles after release * is asserted. 5. the external agent deasserts extrqst * 2 cycles after release * is asserted. this does not apply however to situations where an attempt is made to issue another external request. 6. the external agent sets the sysad bus and syscmd bus to tri-state when processing of the external request is complete. the processor becomes able to issue processor requests 1 cycle after the external agent sets the busses to tri-state. note: the sysadc bus and syscmdp bus timing is the same as that for the sysad bus and syscmd bus, respectively. figure 6.2.18 arbitration protocol relating to external requests master slave master 1 23456 cycle master clock sysad bus validin * wxtrqst * 78910 11 12 syscmd bus cmd release * 1 5 4 3 neod 2 addr data0 6
chapter 6 tx4955a system interface 6-19 6.2.8.8 external read request protocol external read requests are requests that read 1 word of data from processor-internal resources such as registers. external read requests cannot be partitioned. namely, it is not possible to generate other requests between an external read request and the corresponding read response. figure 6.2.19 illustrates the timing of external read requests, which consist of the following steps. 1. the external agent requests use of the system interface by asserting extrqst * . 2. the processor asserts release * for 1 cycle, then releases the system interface by deasserting release * and puts the interface into the slave state. 3. after release * is deasserted, the sysad bus and syscmd bus are set to tri-state for 1 cycle. 4. the external agent sends a read request command to the syscmd bus, sends a read request address to the sysad bus, and asserts validin * for 1 cycle. 5. after sending the above address and command, the external agent sets the syscmd and sysad busses to tri-state, makes it possible for the processor to drive them, then releases them both. the processor that accessed the data to be read returns the data to the external agent. therefore, the processor sends the data identifier to the syscmd bus, sends the response data to the sysad bus, then asserts validout * for 1 cycle. this data identifier indicates that data are the response data of the final data cycle. 6. the system interface is in the master state. the processor continues to drive the syscmd bus and sysad bus even after the read response is returned. note: timing of the sysadc bus and syscmdp bus is the same as that for the sysad and syscmd busses, respectively. external read requests can read data from only a single word in the processor. if data elements other than a word are requested, the processor response is not defined. figure 6.2.19 external read request when system interface is in the master state note: the processor contains no resources that can read by way of external read requests. the processor returns data identifiers with syscmd(5) of the error data bits set along with undefined data when it receives an external read request. 1 23456 cycle master clock sysad bus validin * extrqst * 78910 11 12 syscmd bus release * master 1 5 3 2 slave master addr 6 data0 read 6 data0 validout * 4
chapter 6 tx4955a system interface 6-20 6.2.8.9 external null request protocol the processor only supports one external null request. the system interface release external null request returns the system interface from the slave state to the master state. this request does not affect any other processors. the only processing the external null request does is to have the processor return the system interface to the master state. figure 6.2.20 illustrates the timing of the external null request, which consists of the following steps. 1. the external agent drives the system interface, sends the external null request command to the syscmd bus, then asserts the validin * signal for 1 cycle. 2. the sysad bus is not available during the external null request address cycle (there are no valid data in the bus). 3. the null request ends when the address cycle is issued. in the case of a system interface release null request, the external agent releases the syscmd bus and sysad bus so the system interface can return to the master state. figure 6.2.20 system interface release external null request 1 23456 cycle master clock sysad bus validout * validln * 78910 11 12 syscmd bus extqst * release * slave 3 2 1 unsd sinull master
chapter 6 tx4955a system interface 6-21 6.2.8.10 external write request protocol the same protocol as the processor single word write protocol is used for external write requests, except when the validin * signal is asserted instead of the validout * signal. figure 6.2.21 illustrates the timing of the external write request, which consists of the following steps. 1. the external agent requests use of the system interface by asserting extrqst * . 2. the processor asserts release * , then the system interface is released from the processor and goes into the slave state. 3. the external agent sends a write command to the syscmd bus, and sends a write address to the sysad bus while asserting validin * . 4. the external agent sends data identifiers to the syscmd bus, and sends data to the sysad bus while asserting validin * . 5. data identifiers for this data cycle must contain an indication of a coherent or non-coherent final data cycle. 6. after a data cycle is issued, the write request is complete, the external agent sets the syscmd and sysad busses to tri-state, then the system interface returns to the master state. timing of the sysadc bus and syscmdp bus are each the same as the sysad bus and syscmd bus, respectively. external write requests can write only 1 word of data to the processor. operation of processors that have specified data elements other than a single word of data by an external write request is not defined. figure 6.2.21 external write request when system interface starts in the master state 1 23456 cycle master clock sysad bus validout * validln * 78910 11 12 syscmd bus extrqst * release * master 2 4 3 addr data0 slave master write neod 6 5 1
chapter 6 tx4955a system interface 6-22 6.2.8.11 read response protocol the external agent must use the read response protocol to return data to the processor if a processor read request has been received. the sequence of the read response protocol is as follows. 1. the external agent waits for the processor to automatically execute a shift into the slave state. 2. the external agent uses either a single data cycle or a series of data cycles to return data. 3. after issuing the final data cycle, the read response ends, then the external agent sets the syscmd and sysad busses to tri-state. 4. the system interface returns to the master state. note: after issuing a read response, the processor automatically shifts to the slave state. 5. data identifiers of a data cycle must indicate that the data are response data. 6. final data cycle identifiers must contain an indication that a cycle is the final data cycle. in the case of read responses to non-coherent block read requests, it is not necessary for the response data to check the initial cache state. the cache state is automatically set to exclusively dirty. data identifiers of data cycles can send notification of transfer data errors in those cycles. the external agent must return data blocks with the correct size even when there is an error in the data. whether there is a single error or multiple errors in the read response data cycles, the processor processes them as bus errors. read responses must always be returned to the processor when a processor read request is being held. processor operation is not defined if a read response was returned in a state where there were no processor read requests on hold. figure 6.2.22 illustrates a processor word read request and the subsequent word read response. also, figure 6.2.23 illustrates the read response to a processor block read request when the system interface is in the slave state. note: the sysadc bus and syscmdp bus timing is the same as the sysad bus and syscmd timing, respectively.
chapter 6 tx4955a system interface 6-23 figure 6.2.22 processor word read request and subsequent word read response figure 6.2.23 block read response when system interface is in the slave state 1 23456 cycle master clock sysad bus validout * validin * 78910 11 12 syscmd bus extrqst * master 3 slave master addr data0 addr neod 4 2 release * 1 6 1 23456 cycle master clock sysad bus validout * validin * 78910 11 12 syscmd bus extrqst * master 3 slave master addr data3 addr neod 4 2 release * 6 data1 data2 data0 ndata ndata ndata 5
chapter 6 tx4955a system interface 6-24 6.2.9 data transfer the maximum data transfer rate of the system interface is 1 double word per cycle. the external agent can select the data transfer rate to the processor. for example, it is possible to transfer data and assert the validin * signal just once for every n cycles instead of at all cycles. the external agent can transfer data to the processor at the selected transfer rate. the processor interprets cycles as being valid when the validin * signal is asserted and the syscmd bus includes the data identifier. after a cycle has been interpreted as valid, the processor continues to accept data until a data word with an indication that it is the final data word appears. 6.2.9.1 data transfer pattern the term ?data pattern? in the case of block write operations, refers to a string of text that indicates the ?data? cycles repeated so that the appropriate data transfer speed can be obtained and the ?unused? cycles. dxx data patterns indicate a repetition data transfer rate where there is one double word in three cycles followed by two unused cycles. the data transfer rate is set by g2sconfig register(0xf ff10 0000). table 6.2.5 indicates the data transfer rate, data pattern, and setting. table 6.2.5 data transfer rate, data pattern and setting at block write requests maximum data transfer rate data pattern setting bit0 1 double word/3 master clock cycle dxx 0 1 double word/1 master clock cycle d 1 note: the setting bit0 is bit0 of the g2sconfig register (0xf ff10 0000). bit0 is set to ?0? when initialized. 6.2.9.2 independent transfer on sysad bus a majority of applications connect the processor and external agent interior (both directions), and register format transceivers together in a point-to-point manner via the sysad bus. the only two sysad bus drives available for such applications are the processor and the external agent. depending on the application, it may be necessary to make additional connections on the sysad bus for drivers and receivers to transfer data using the sysad bus without involving the processor. such transfers are referred to as independent transfers. in order to perform independent transfers, the external agent must use arbitration handshake signals and external null requests to properly tune sysad bus control. independent transfer is performed on the sysad bus according to the following steps. 1. the external agent requests access to the sysad bus in order to issue an external request. 2. the processor releases the system interface and puts it in the slave state. 3. the external agent can independently transfer data using the sysad bus. however, the validin * signal must be asserted during that transfer. 4. when transfer is complete, the external agent must issue a system interface release null request and return the system interface to the master state.
chapter 6 tx4955a system interface 6-25 6.2.10 system interface cycle time in the case of a processor, there is a response time for each kind of processor transaction and for each external request. a minimum and maximum cycle count has been prescribed for each response time. since processor requests themselves are restrained by system interface request protocols, checking the protocols makes it possible to determine the cycle count required for requests. the interval for the next interface operation is variable within the range of the minimum and maximum cycle counts. ? stand-by time from when an external request is received and the processor releases the system interface, until when the interface enters the slave state (release latency). ? response time to external request that requires a response (external response latency). 6.2.10.1 release latency broadly defined, release latency is the number of cycles for which it is possible to wait from when the processor receives an external request until when the system interface is released and shifts to the slave state. if there are no processor requests currently in progress, the processor must delay release of the system interface for a few cycles since it is internal operation. therefore, if release latency is strictly defined, it becomes the cycle count from when the extrqst * signal is asserted until when the release * signal is asserted. there are three types of release latency. ? category 1: if external request signal is asserted 2 cycles before the final cycle of the processor request ? category 2: if external request signal is asserted during processor request or is the final cycle even if it is asserted ? category 3: if processor automatically shifts to the slave state table 6.2.6 indicates the minimum and maximum release latency inherent to categories 1, 2, and 3. however, note that these cycle counts may be changed at any time. table 6.2.6 release latency for external requests category minimum cycle count maximum cycle count 13 5 21 24 30 0
chapter 6 tx4955a system interface 6-26 6.2.11 system interface command and data identifiers system interface commands specify the type of system interface and its properties. this specification is performed in the request address cycle. the system interface data identifiers specify the properties of the data transferred during the system interface data cycle. of the system interface commands and data identifiers used for external requests, set the bits and fields that are reserved to ?1.? in the case of system interface commands and data identifiers used for processor requests, bits, field contents and data identifiers that are reserved in the commands are undefined. 6.2.11.1 syntax of commands and data identifiers system interface commands and data identifiers consist of 9 bits. these commands are sent by the syscmd bus from the processor to the external agent or from the external agent to the processor during either the address cycle or the data cycle. bit 8 (msb) of the syscmd bus specifies whether the syscmd contents at that time are a command or a data identifier (namely, whether the current cycle is an address cycle or a data cycle). if the contents are a system interface command, then syscmd(8) must be set to ?0.? if the contents are a system interface data identifier, then syscmd(8) must be set to ?1.? 6.2.11.2 syntax of system interface commands following is an explanation of the syscmd bus structure in the case of a system interface command. figure 6.2.24 illustrates the structure common to all system interface commands. 87 54 0 0 request type request specific figure 6.2.24 syntax bit structure of system interface command syscmd(8) must always be set to ?0? in the case of system interface commands. syscmd(7:5) specifies the type of system interface request (read, write, null). table 6.2.7 indicates the syscmd(7:5) specification method. table 6.2.7 syscmd(7:5) specification method for system interface commands syscmd(7:5) command 0 read request 1 reserve 2 write request 3 null request 4 7 reserve syscmd(4:0) varies depending on the type of request. each specification type is indicated below.
chapter 6 tx4955a system interface 6-27 6.2.11.3 read requests figure 6.2.25 illustrates the syscmd format in the case of read requests. 87 54 0 0 000 read request specific figure 6.2.25 bit definition of syscmd bus for read requests table 6.2.8, 6.2.9, and 6.2.10 indicate the methods for specifying syscmd(4:0) for read requests. table 6.2.8 specification method of syscmd(4:3) for read requests syscmd(4:3) read properties 0 1 reserved 2 non-coherent block read 3 word or partial word read table 6.2.9 specification method of syscmd(2:0) for block read requests syscmd(2) reserved syscmd(1:0) read block size 0 reserved 18 words 2 3 reserved table 6.2.10 data size expressed by syscmd(2:0) for double word, partial double word, word or partial word read requests syscmd(2:0) read data size 0 1 byte valid (byte) 1 2 bytes valid (half-word) 2 3 bytes valid (tri-byte) 3 4 bytes valid (word) 4 5 bytes valid (quinti-byte) 5 6 bytes valid (sexi-byte) 6 7 bytes valid (septi-byte) 7 8 bytes valid (double word) note: 6.10.4 of syscmd(2:0) is only valid when in the 64-bit bus mode.
chapter 6 tx4955a system interface 6-28 6.2.11.4 write requests figure 6.2.26 illustrates the syscmd format for write requests. table 6.2.11 indicates the methods of specifying write properties using syscmd(4:3). table 6.2.12 indicates the methods of specifying replacements properties using syscmd(2:0) for block write requests. table 6.2.13 indicates the methods of specifying the data size using syscmd(2:0) for write requests. 87 54 0 0 010 write request specific figure 6.2.26 syscmd bus bit specification for write requests table 6.2.11 methods of specifying syscmd(4:3) for write requests syscmd(4:3) write properties 0 1 reserved 2 block write 3 word or partial word write table 6.2.12 specification method of syscmd(2:0) for block write requests syscmd(2) reserved syscmd(1:0) write block size 0 reserved 18 words 2 3 reserved table 6.2.13 methods for specifying syscmd(2:0) for word or partial word write requests syscmd(2:0) write data size 0 1 byte valid (byte) 1 2 bytes valid (half-word) 2 3 bytes valid (tri-byte) 3 4 bytes valid (word) 4 reserved 5 reserved 6 reserved 7 reserved
chapter 6 tx4955a system interface 6-29 6.2.11.5 null requests figure 6.2.27 illustrates the syscmd format in the case of read requests. 87 54 0 0 011 null request specific figure 6.2.27 bit definition of the syscmd bus for null requests null request commands are always used for system interface release external null requests. table 6.2.14 indicates methods of specifying syscmd(4:3) for system interface release external null requests. syscmd(2:0) is reserved for null requests. table 6.2.14 method of specifying syscmd(4:3) for external null requests syscmd(4:3) null properties 0 release system interface 1 3 reserved 6.2.11.6 syntax of system interface data identifiers this section defines methods of specifying the syscmd bus for system interface identifiers. the bit structure illustrated in figure 6.2.28 is common to all system interface data identifiers. 87 543 0 0 final data response data error data data check reserved figure 6.2.28 bit definition of the syscmd bus for null requests syscmd(8) must always be set to ?1? for system interface data identifiers. system interface data identifiers are in the non-coherent data format. 6.2.11.7 non-coherent data non-coherent data are data such as the following. ? data that are the subject of a processor block write request or a processor double word/partial double word/word/partial word write request. ? data that are returned to a processor non-coherent block read request or a processor double word/ partial double word/word/partial word read request. ? data that are the subject of an external write request. ? data that are returned to an external read request as a response.
chapter 6 tx4955a system interface 6-30 6.2.11.8 bit definition of data identifiers in the case of processor or external coherent data identifiers and processor or external non-coherent data identifiers, syscmd(7) indicates that they are the final data element, and syscmd(6) indicates whether they are response data. response data are the data that are returned to a read request as a response. syscmd(5) indicates whether there is an error in a data element. uncorrectable errors are included in the error data. when such an error is returned to the processor, a bus error is generated. if a primary parity error is detected in the data items to be transferred, the processor deasserts the good data bits and sends data. syscmd(4) indicates to the processor whether the data bits and check bits of a data element should be searched. syscmd(3) is reserved in the case of external data identifiers. syscmd(4:3) is reserved in the case of non-coherent processor data identifiers. syscmd(2:0) is reserved in the case of non-coherent data identifiers. table 6.2.15 indicates methods of specifying syscmd(7:3) for processor data identifiers. table 6.2.16 indicates methods of specifying syscmd(7:3) for external data identifiers. table 6.2.15 methods of specifying syscmd(7:3) for processor data identifiers syscmd(7) final data element indication 0 final data element 1 is not final data element syscmd(6) response data indication 0 response data 1 is not response data syscmd(5) good data indication 0 no errors 1 is error data syscmd(4:3) reserved table 6.2.16 method of specifying syscmd(7:3) for external data identifiers syscmd(7) final data element indication 0 final data element 1 is not final data element syscmd(6) response data indication 0 response data 1 is not response data syscmd(5) good data indication 0 no errors 1 is error data syscmd(4) enable data check 0 check data bits and check bits 1 do not check data bits and check bits syscmd(3) reserved
chapter 6 tx4955a system interface 6-31 6.2.12 system interface addresses system interface addresses are complete 32-bit physical addresses. they are sent to the lower 32 bits of the sysad bus during the address cycle. 6.2.12.1 addressing rules in the 32-bit bus mode addresses that are to be used in word or partial word transactions are arranged to match the size of the data element. the following rules are used by this system. ? target addresses of the block request are aligned to the word boundaries. in other words, the lower 2 bits of the address become ?0?. ? word requests set the lower 2 bits of the address to ?0?. ? half-word requests set the least significant bit of the address to ?0?. ? byte requests and 3-byte requests use the byte address. 6.2.13 mode register of system interface (g2sconfig) the mode register of system interface ( g2sconfig ) is a read/write register. this register is only word-access. table 6.2.17 g2sconfig address field description 0xf_ff10_0000 g2sconfig mode register of system interface 31 20 19 4 3 2 1 0 bit reserved tout val tout enable write mode data rate bit field description coldreset read/write 31..20 ? reserved undefined read 19..4 tout val set data of read time out counter 0x0: generate read time out error other 0x0: not generate read time out error 0xffff read/write 3 tout enable enable bit of read time out counter in case of mode43 * = h, read time out counter does not work. we recommend it to write 0 or the value of read data. 0 read/write 2..1 write mode processor write protocols set 00: r4000 compatible write 01: reserved 10: pipeline write 11: reissue write 00 read/write 0 data rate at the block write data rate set 0: awwwwwwww 1: awxxwxxwxxwxx wxxwxxwxxwxx 0 read/write note1: when initialized single write: adxx (r4000 compatible) block write: adddd note2: in case of mode43 * = h, read time out counter does not work. it can generate read time out error when wrote in 0x0 at tout val. it does not let a value of tout enable affect it. please write in a value except 0x0 at tout val. figure 6.2.29 g2sconfig register formats
chapter 6 tx4955a system interface 6-32 6.2.14 data error detection the tx4955a internal system interface uses the following two methods to detect data errors: ? indication of good data by data identifier syscmd(5) ? determination by a check bit 6.2.14.1 indication of good data by data identifier syscmd(5) this bit indicates whether data is good or not for all data. therefore, in a block refill transfer, for example, no matter in what number of data syscmd(5) may have been set, a bus error exception is always generated. 6.2.14.2 determination by a check bit when an error is detected by check bit determination, a bus error exception occurs. because this determination also is made for all data, no matter in what number of data in a block refill transfer an error may have occurred, a bus error exception is always generated. 6.2.14.3 timing at which a bus error exception occurs indication of good data (syscmd(5)): two cycles after read data check bit error detection: three cycles after read response data 6.2.14.4 precautions ? there is no means of identifying whether a bus error exception has been generated by indication of good data or by check bit determination. nor does the tx49 core have a cache parity bit, but when a bus error exception occurs during a block refill transfer, the cache line is referenced invalid. ? regardless of whether a bus error exception has been generated by indication of good data or by check bit determination during a block refill transfer, a designated block size of data needs to be transferred.
chapter 6 tx4955a system interface 6-33 6.3 system interface of tx4300 type protocol mode in tx4955a, it is built in system interface function corresponding to tx4300 type protocol. a selection of above-mentioned r5000 type protocol mode or tx4300 type protocol mode increases by external pin (mode43 * : 117 pin). mode43 * = 0: tx4300 type protocol mode43 * = 1: r5000 type protocol note: in tx4300 type protocol mode of tx4955a, there is not preq signal. therefore there is the need that preq terminal of an external agent is always fixed in "l" level. and there is not a function too to show that protocol errors were detected. but search of protocol errors is possible when i have a counter built-in in tx4955a inside, and there is not lead reply between constant time because it is established the function that an exception generates bus error. 6.3.1 system interface description of tx4300 type protocol mode the tx4955a processor has a 32-bit address/data interface. the system interface consists of: ? 32-bit address and data bus, sysad sysad sysad sysad ? 5-bit command bus, syscmd syscmd syscmd syscmd ? five handshake signals: ? evalid evalid evalid evalid * , pvalid , pvalid , pvalid , pvalid * ? ereq ereq ereq ereq * ? pmaster pmaster pmaster pmaster * , eok , eok , eok , eok * table 6.3.1 system interface signals (tx4300 type protocol mode is mode43 * = 0) signal i/o function sysad (31:0) i/o address and data transfer bus, multiplexed between the processor and an external agent. syscmd (4:0) i/o used for command and data identifier transmission between the processor and an external agent. syscmd (8:5) / gnd o when tx4300 type protocol mode, those pin output ?l?. sysadc (3:0) / gnd o when tx4300 type protocol mode, those pin output ?l?. syscmdp / gnd o when tx4300 type protocol mode, this pin output ?l?. validin * / evalid * i during the cycle it is asserted, evalid * indicates an external agent is driving a valid address or valid data on the sysad bus, and a valid command or data identifier on the syscmd bus. validout * / pvalid * o during the cycle it is asserted, pvalid * , indicates the processor is driving a valid address or valid data on the sysad bus, and a valid command or data indentifier on the syscmd bus. extrqst * / ereq * i indicates an external agent is requesting system interface bus ownership. release * / pmaster o indicates an external agent is capable of the system interface bus. wrrdy * / eok * i indicates an external agent is capable of accepting a processor request. rdrdy * / gnd o when tx4300 type protocol mode this pin output ?l?.
chapter 6 tx4955a system interface 6-34 table 6.3.2 pin assign (mode43 * = 0) 1 vss 41 vss 81 vccint 121 sysad28 2 bufsel1 42 trst * 82 nmi * 122 sysad29 3jtdo 43 rdrdy * / gnd 83 extrqst * / ereq * 123 vccint 4jtdi 44 wrrdy * / eok * 84 reset * 124 vss 5jtck 45 validin * / evalid * 85 coldreset * 125 sysad30 6jtms 46 validout * / pvalid * 86 vccio 126 vccio 7vccio 47 release * / pmaster * 87 endian 127 vss 8 vss 48 vccio 88 vccio 128 sysad31 9sysad4 49 pllreset * 89 vss 129 sysadc2 / gnd 10 sysad5 50 vccint 90 sysad16 130 vccint 11 vccint 51 tintdis 91 vccint 131 vss 12 vss 52 vss 92 vss 132 sysadc3 / gnd 13 sysad6 53 syscmd0 93 sysad17 133 vccio 14 vccio 54 syscmd1 94 sysad18 134 vss 15 vss 55 syscmd2 95 vccio 135 sysadc0 / gnd 16 sysad7 56 syscmd3 96 vss 136 vccint 17 sysad8 57 syscmd4 97 sysad19 137 vss 18 vccint 58 syscmd5 / gnd 98 vccint 138 sysadc1 / gnd 19 vss 59 vccio 99 vss 139 sysad0 20 sysad9 60 vss 10 sysad20 140 vccio 21 vccio 61 syscmd6 / gnd 10 sysad21 141 vss 22 vss 62 syscmd7 / gnd 10 vccio 142 sysad1 23 sysad10 63 syscmd8 / gnd 10 vss 143 sysad2 24 sysad11 64 syscmdp / gnd 10 sysad22 144 vccint 25 vccint 65 vccint 10 vccint 145 vss 26 vss 66 vss 10 vss 146 sysad3 27 sysad12 67 vccio 10 sysad23 147 pcst8 28 vccio 68 halt/doze 10 sysad24 148 pcst7 29 vss 69 int0 * 10 vccio 149 pcst6 30 sysad13 70 int1 * 11 vss 150 pcst5 31 sysad14 71 int2 * 11 sysad25 151 pcst4 32 vccint 72 int3 * 11 vccint 152 vccio 33 vss 73 int4 * 11 vss 153 vss 34 sysad15 74 int5 * 11 sysad26 154 vccio 35 bufsel0 75 vccio 11 sysad27 155 vsspll 36 pcst3 76 vss 11 vccio 156 pllcap 37 pcst2 77 tpc3 11 mode43 * 157 vccpll 38 pcst1 78 tpc2 11 divmode1 158 vss 39 pcst0 79 tpc1 11 divmode0 159 masterclock 40 vccio 80 dclk 12 vss 160 vccio note: ? * ? means the signal is the low-active. mode43 * = 0: tx4300 type = 1: r5000 type gnd means out to low level when mode43 * = 0
chapter 6 tx4955a system interface 6-35 6.3.2 system events system events include: ? fetch miss in the instruction cache ? load miss in the data cache ? store miss in the data cache ? an uncached load or store ? actions resulting from the execution of cache instructions when a system event occurs, the processor issues a request or a series of requests through the system interface to access some external resource to service that event. the system interface must be connected to an external agent that coordinates access to system resources. processor requests include both read and write requests: ? a read request supplies an address to an external agent ? a write request supplies an address and a word or block of data to be written to an external agent processor read requests that have been issued, but for which data has not yet been returned, are said to be pending . the processor will not issue another request while a read is already pending. a processor read request is said to be complete after the last transfer of response data has been received from an external agent. a processor write request is said to be complete after the last word of data has been transmitted. external requests include both read responses and write requests: ? a read response supplies a block or single transfer of data from an external agent in response to a read request ? a write request supplies an address and a word of data to be written to a processor resource when an external agent receives a read request, it accesses the specified resource and returns the requested data through a read response, which may be returned any time after the read request and at any data rate. by default, the processor is the master of the system interface. an external agent becomes master of the system interface either through arbitration, or by default after a processor read request. the external agent returns mastership to the processor after the external request completes and/or after the processor read request has been serviced. 6.3.3 system event sequences and the sysad bus protocol the following sections detail the sequence and timing of processor and external requests. note: the following sections describe the sysad bus protocol ; the tx4955a processor always meets the conditions of this protocol. the tx4955a processor is capable of receiving sequences of transactions on the bus at full protocol speed and of receiving data on every cycle. at a minimum, the design of external agents must meet the requirements of this protocol, and would ideally take full advantage of the maximum speed of the tx4955a processor. 6.3.3.1 fetch miss when the processor misses in the instruction cache on a fetch, it obtains a cache line of instructions from an external agent. the processor issues a read request for the cache line and waits for an external agent to provide the data in response to this read request.
chapter 6 tx4955a system interface 6-36 6.3.3.2 load miss when the processor misses in the data cache on a load, it obtains a cache line of data from an external agent. the processor issues a read request for the cache line and waits for an external agent to provide the data in response to this read request. if the cache data which the incoming line will replace contains valid dirty data, this data is written to memory. the read completes before the write of the dirty cast-out data. 6.3.3.3 store miss when the processor misses in the data cache on a store, it issues a read request to bring a cache line of data into the cache, where it is then updated with the store data. if the cache data which the incoming line will replace contains valid dirty data, the data is written to memory. the read completes before the write of the dirty cast-out data. to guarantee that cached data written by a store is consistent with main memory, the corresponding cache line must be explicitly flushed from the cache using a cache operation. 6.3.3.4 uncached load or store when the processor performs an uncached load, it issues a read request and waits for a single transfer of read response data from an external agent. when the processor performs an uncached store, it issues a write request and provides a single transfer of data to the external agent. the processor does not consolidate data on uncached writes. for example, writes of two contiguous halfwords takes two write cycles, they are never grouped into a single word write. 6.3.3.5 cache instructions the tx4955a processor provides a number of cache instructions for use in maintaining the state and contents of the caches. cache operations supported in the tx4955a processor are described in chapter 5. 6.3.3.6 byte ordering (endian) the system interface byte order is set by the endian endian endian endian of external pin. the byte order is big-endian when endian endian endian endian is high, and little-endian when endian endian endian endian is low. the re (reverse-endian) bit in the status register can be set by software to reverse the byte order available in user mode. 6.3.3.7 physical addresses physical addresses are driven on sysad (31:0) sysad (31:0) sysad (31:0) sysad (31:0) during address cycles. 6.3.3.8 interface buses figure 6.3.1 shows the primary communication paths for the system interface: a 32-bit address and data bus, sysad (31:0) sysad (31:0) sysad (31:0) sysad (31:0), and a 5-bit command bus, syscmd (4:0) syscmd (4:0) syscmd (4:0) syscmd (4:0). these sysad sysad sysad sysad and the syscmd syscmd syscmd syscmd buses are bidirectional; that is, they are driven by the processor to issue a processor request, and by the external agent to issue an external request. a request through the system interface consists of: ? an address ? a system interface command that specifies the precise nature of the request ? a series of data elements if the request is for a write or read response.
chapter 6 tx4955a system interface 6-37 tx4955a syscmd (4:0) sysad (31:0) external agent figure 6.3.1 system interface buses 6.3.3.9 address and data cycles the syscmd syscmd syscmd syscmd bus identifies the contents of the sysad sysad sysad sysad bus during any cycle in which it is valid. cycles in which the sysad sysad sysad sysad bus contains a valid address are called address cycles . cycles in which the sysad sysad sysad sysad bus contains valid data are called data cycles . the most significant bit of the syscmd syscmd syscmd syscmd bus is always used to indicate whether the current cycle is an address cycle or a data cycle. when the tx4955a processor is driving the sysad sysad sysad sysad and syscmd syscmd syscmd syscmd buses, the system interface is in master state . when the external agent is driving the sysad sysad sysad sysad and syscmd syscmd syscmd syscmd buses, the system interface is in slave state . ? when the processor is master, it asserts the pvalid pvalid pvalid pvalid * signal when the sysad sysad sysad sysad and syscmd syscmd syscmd syscmd buses are valid. ? when the processor is slave, an external agent asserts the evalid evalid evalid evalid * signal when the sysad sysad sysad sysad and syscmd syscmd syscmd syscmd buses are valid. the syscmd syscmd syscmd syscmd bus identifies the contents of the sysad sysad sysad sysad bus during valid cycles. ? during address cycles [syscmd (4) syscmd (4) syscmd (4) syscmd (4) = 0], the remainder of the syscmd syscmd syscmd syscmd bus, syscmd (3:0) syscmd (3:0) syscmd (3:0) syscmd (3:0), contains a system interface command , described later in this chapter. ? during data cycles [syscmd (4) syscmd (4) syscmd (4) syscmd (4) = 1], the remainder of the syscmd syscmd syscmd syscmd bus, syscmd (3:0) syscmd (3:0) syscmd (3:0) syscmd (3:0), contains a data identifier , described later in this chapter.
chapter 6 tx4955a system interface 6-38 6.3.4 system interface protocols figure 6.3.2 shows the register-to-register operation of the system interface. that is, processor outputs come directly from output registers and begin to change with the rising edge of sclock sclock sclock sclock.? processor inputs are fed directly to input registers that latch these input signals with the rising edge of sclock sclock sclock sclock. this allows the system interface to run at the highest possible clock frequency. tx4955a sclock input data output data figure 6.3.2 system interface register-to-register operation 6.3.4.1 master and slave states when the tx4955a processor is driving the sysad sysad sysad sysad and syscmd syscmd syscmd syscmd buses, the system interface is in master state . when the external agent is driving the sysad sysad sysad sysad and syscmd syscmd syscmd syscmd buses, the system interface is in slave state . in master state, the processor asserts the signal pvalid pvalid pvalid pvalid * whenever the sysad sysad sysad sysad and syscmd syscmd syscmd syscmd buses are valid. in slave state, the external agent asserts the signal evalid evalid evalid evalid * whenever the sysad sysad sysad sysad and syscmd syscmd syscmd syscmd buses are valid. 6.3.4.2 moving from master to slave state the processor is the default master of the system interface. an external agent becomes master of the system interface through arbitration, or by default after a processor read request. the external agent returns mastership to the processor after an external request completes. the system interface remains in master state unless one of the following occurs: ? the external agent requests and is granted the system interface (external arbitration). ? the processor issues a read request (uncompelled change to slave state). the following sections describe these two actions. ? sclock sclock sclock sclock is an internal clock used by the processor to sample data at the system interface and to clock data into the processor system interface output registers.
chapter 6 tx4955a system interface 6-39 6.3.4.3 external arbitration the system interface must be in slave state for the external agent to issue an external request through the system interface. the transition from master state to slave state is arbitrated by the processor using the system interface handshake signals ereq ereq ereq ereq * and pmaster pmaster pmaster pmaster * . this transition is described by the following procedure: 1. an external agent signals that it wishes to issue an external request by asserting ereq ereq ereq ereq * . 2. when the processor is ready to accept an external request, it releases the system interface from master to slave state by negating pmaster pmaster pmaster pmaster * . 3. the system interface returns to master state as soon as the issue of the external request is complete. 6.3.4.4 uncompelled change to slave state an uncompelled change to slave state is the transition of the system interface from master state to slave state, initiated by the processor itself when a processor read request is pending. pmaster pmaster pmaster pmaster * is negated automatically after a read request. an uncompelled change to slave state occurs either during or some number of cycles after the issue cycle of a read request. the uncompelled release latency depends on the state of the cache. after an uncompelled change to slave state, the processor returns to master state at the end of the next external request. this can be a read response, or some other type of external request. an external agent must note that the processor has performed an uncompelled change to slave state and begin driving the sysad sysad sysad sysad bus along with the syscmd syscmd syscmd syscmd bus. as long as the system interface is in slave state, the external agent can begin an external request without arbitrating for the system interface; that is, without asserting ereq ereq ereq ereq * . after the external request, the system interface returns to master state. 6.3.4.5 signal timing the system interface protocol describes the cycle-by-cycle signal transitions that occur on the pins of the system interface to realize requests between the processor and an external agent. figure 6.3.3 shows the timing relationships between system interface signal edges.
chapter 6 tx4955a system interface 6-40 t ds t do t dh t do t dh t ds t do valid output valid input valid input note: these waveforms only describe edge-to-edge timing relationships. evalid * , ereq * , eok * , int * , nmi * pvalid * pmaster * sysad sysadc syscmd syscmdp sclock figure 6.3.3 system interface edge timing relationships the timing summary section below describes the minimum and maximum timing values of each signal. the sections that follow describe the timing requirements for various bus cycles. 6.3.5 timing summary in the following timing diagrams, gray-scale signals indicate values that are either unknown or don?t cares, within the specification limits. they may be any value as long they do not violate any bus value or timing specification. the timing diagrams illustrate cycles using the following signals: ? pmaster pmaster pmaster pmaster * ? evalid evalid evalid evalid * ? pvalid pvalid pvalid pvalid * ? eok eok eok eok * ? ereq ereq ereq ereq * pmaster pmaster pmaster pmaster * (o) indicates the processor is the master of the system interface bus. extagent cmd extagent data proc cmd proc data syscmd sysad scycle c b a pmaster* sclock figure 6.3.4 sample cycle with pmaster * asserted, then deasserted a processor drives sysad and syscmd buses (processor is master). bpmaster pmaster pmaster pmaster is deasserted. sysad and syscmd buses are set to a tri-state(no bus master). c external agent drives sysad and syscmd buses (external agent is master).
chapter 6 tx4955a system interface 6-41 extagent cmd extagent data proc cmd proc data c b a pmaster * syscmd sysad scycle sclock figure 6.3.5 sample cycle with pmaster * asserted a external agent drives sysad and syscmd buses (external agent is master). b sysad and syscmd buses are set to a tri-state (no bus master). cpmaster pmaster pmaster pmaster * is asserted. processor drives sysad and syscmd buses (processor is master). evalid evalid evalid evalid * (i), pvalid (i), pvalid (i), pvalid (i), pvalid * (o) (o) (o) (o) during a cycle in which either signal is asserted, the signal indicates a new valid address or valid data is on the sysad bus, and a new valid command or data identifier is on the syscmd bus. evalid evalid evalid evalid * indicates an external agent is driving new sysad and syscmd values. pvalid pvalid pvalid pvalid * indicates the processor is driving new sysad and syscmd values. data a sysad scycle sclock cmd syscmd evalid or pvalid figure 6.3.6 sample cycle with pvalid * and evalid * a: new sysad and syscmd values. each cycle either of these signals remains asserted indicates there is a new sysad and syscmd value. data data b a sysad scycle sclock cmd cmd syscmd evalid * or pvalid * figure 6.3.7 sample cycles with multiple pvalid * and evalid * a new sysad and syscmd value. b another new sysad and syscmd value.
chapter 6 tx4955a system interface 6-42 eok eok eok eok * (i) (i) (i) (i) indicates an external agent accepts a processor request. an external agent has excepted the processor read/write command if and only if the following has occurred: aeok eok eok eok * is active. b the processor asserts pvalid pvalid pvalid pvalid * and drives a read or write command. eok eok eok eok * is asserted and the external agent accepts the processor command. once the external agent has accepted a processor write command, the agent must be able to accept the entire data size at the programmed data rate immediately following this command. the external agent may provide read response data to the processor at any rate. deasserting eok may kill a processor read/write request in progress. if this occurs, the external agent must ignore command and data from the processor in the following cycle. pro cmd (rd/wr) proc address c b a sysad scycle sclock syscmd eok * pvalid * figure 6.3.8 sample cycle with eok * asserted proc address pro cmd (wr) proc data data cmd d c b a sysad scycle sclock syscmd eok * pvalid * figure 6.3.9 sample cycle with eok * asserted, then deasserted aeok eok eok eok * is active. b processor asserts pvalid pvalid pvalid pvalid * and drives a read or write command. eok eok eok eok * is deasserted (external agent has killed the processor?s command). c the external agent must ignore any sysad and syscmd data from the processor. d the external agent does not ignore any sysad and syscmd data from the processor.
chapter 6 tx4955a system interface 6-43 ereq ereq ereq ereq * ( ( ( (i) i) i) i) indicates an external agent is requesting bus ownership of the system interface. to gain mastership of the bus, an external agent must arbitrate with the processor as follows: a external agent asserts ereq * b wait for pmaster * to be deasserted (1 to n cycles). c external agent drives sysad and syscmd buses. the external agent is guaranteed to maintain mastership of the bus as long as ereq ereq ereq ereq is asserted. if at any time ereq ereq ereq ereq * is deasserted, the external agent must go back to step a and re-arbitrate for the bus. extagent cmd extagent data c b a sysad scycle sclock syscmd ereq * pmaster * figure 6.3.10 sample cycle with ereq * asserted from the time that ereq ereq ereq ereq * is asserted, the external agent is guaranteed to gain mastership of the bus after at most one processor request. however, if eok eok eok eok * is being deasserted, the external agent will gain mastership of the bus without having to accept any processor requests. the external agent relinquishes bus mastership by deasserting ereq ereq ereq ereq * as shown below: extagent cmd extagent data proc data data cmd c b a sysad scycle sclock syscmd ereq * pmaster * figure 6.3.11 sample cycle with deassertion of ereq * a external agent deasserts ereq ereq ereq ereq * and external agent drives the bus. b bus is set to a tristate. c processor regains mastership of bus. except for a processor read request (see below), assertion of ereq ereq ereq ereq * is the only way the external agent gets and maintains bus mastership.
chapter 6 tx4955a system interface 6-44 read cmd address end of data data d c b a evalid * eok * sysad scycle sclock syscmd pvalid * pmaster * figure 6.3.12 sample cycle with assertion of ereq a processor drives a valid read command and an external agent accepts it. bpmaster pmaster pmaster pmaster * is deasserted and the bus is set to a tristate. c external agent drives last of requested data. during all cycles between b and c the external agent is guaranteed mastership of the bus.
chapter 6 tx4955a system interface 6-45 6.3.6 arbitration the processor is the default master of the bus. it relinquishes ownership of the bus either when an external agent requests and is granted the system interface, or until the processor issues a read request. the transition from processor master to processor slave state is arbitrated by the processor, using the system interface handshake signals ereq ereq ereq ereq * and pmaster pmaster pmaster pmaster * . when a processor read request is pending, the processor transitions to slave state by deasserting pmaster pmaster pmaster pmaster * , allowing an external agent to return the read response data. the processor remains in slave state until the external agent issues an end of data read response, whereupon the processor reassumes mastership, signalled by the assertion of pmaster pmaster pmaster pmaster * . note that an external agent is able to retain mastership of the bus after an end of data read response if the external agent arbitrates for mastership using ereq ereq ereq ereq * . when the processor is master, an external agent acquires control of the system interface by asserting ereq ereq ereq ereq * , and waiting for the processor to deassert pmaster pmaster pmaster pmaster * . the processor is ready to enter slave state when it deasserts pmaster pmaster pmaster pmaster * . the external agent must go through a three-step arbitration process (see the ereq ereq ereq ereq * cycle in the timing summary) before driving the bus. once the external agent has become master through ereq ereq ereq ereq * arbitration, it can remain master as long as it continues to assert ereq ereq ereq ereq * . the system interface returns to master state (with the processor driving the bus) two cycles after ereq ereq ereq ereq * is deasserted. figure 6.3.13 illustrates an arbitration for external requests. external agent command external agent data 812 611 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd ereq * pmaster * figure 6.3.13 external request arbitration when an external agent is master, it may always respond to a read with data. if the external agent has become master by ereq ereq ereq ereq * , it may issue transactions at will; that is, the processor must always accept any command or data on the bus at any time. there is no means for the processor to hold off the external agent once the external agent is master. if the processor is in slave state and needs the bus,wait untile the external agent ereq * deasserted. thereafter, when the processor sees ereq ereq ereq ereq * deasserted, it resumes bus ownership, asserts the pmaster pmaster pmaster pmaster * line, and issues its own command. the processor becomes master and drives the bus two cycles after ereq ereq ereq ereq * is deasserted. an illustration of a processor request for bus mastership and the release of the bus by the external agent is illustrated in figure 6.3.14.
chapter 6 tx4955a system interface 6-46 processor command agent command agent data external external processor address/data 812 611 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd eok * ereq * pmaster * figure 6.3.14 processor request for bus arbitration and external agent release upon assertion of reset reset reset reset * or coldreset coldreset coldreset coldreset * , the processor becomes bus master and the external agent must become slave. this protocol guarantees that either the processor or an external agent is always bus master. the master should never tristate the bus, except when giving up ownership of the bus under the rules of the protocol. 6.3.7 issuing commands when the processor is master of the bus and wishes to issue a command, it cannot successfully issue the command until the external agent signals that it is ready to accept it. this readiness is indicated by assertion of the eok eok eok eok * signal. being master, the processor may place the command on the bus and continually reissue it while waiting for eok eok eok eok * to be asserted; however, the command is not considered issued until eok eok eok eok * has been asserted for two consecutive cycle (see the timing summary for eok eok eok eok * earlier in this chapter). if the eok eok eok eok * signal is asserted in one cycle and then deasserted in the next, during which time a command is issued, that command is considered killed and must be retried. when a command is killed in this way, the processor begins to execute the read/write command. this action must be ignored by the external agent. if a write command is killed, the data cycle following this killed transaction must be ignored. if a read is killed, the processor releases the bus one cycle after and (assuming no ereq ereq ereq ereq * ) regains mastership two cycles later. this allows the processor to retry the transaction. 6.3.8 processor write request a processor write request is issued by the following: ? driving a write command on the syscmd bus ? driving a write address on the sysad bus ? asserting pvalid pvalid pvalid pvalid * for one cycle ? driving the appropriate number of data identifiers on the syscmd bus ? driving data on the sysad bus ? asserting pvalid pvalid pvalid pvalid *
chapter 6 tx4955a system interface 6-47 for 1-to 4-byte writes, a single data cycle is used. 5-, 6- and 7-byte writes are broken up into two address/data transactions; one 4 bytes in size, the next handling the remaining 1, 2, or 3 bytes. for all transactions larger than 7 bytes (e.g. 8, 16, 32), 4 bytes are sent on each data cycle until the appropriate number of bytes has been transferred. the final data cycle is tagged as end of data (eod) on the command bus. to be fully compliant with all implementations of this protocol, an external agent should be able to receive write data over any number of cycles with any number of idle cycles between any two data cycles. however, for the tx4955a processor implementation, data begins to arrive on the cycle immediately following the write issue cycle, and continues to arrive at a programed data rate thereafter. the processor drives data at the rate specified by the data rate configuration signals (see the section describing data rate control, later in this chapter). writes may be cancelled and retried with the eok eok eok eok * signal (see the section earlier, issuing commands). figure 6.3.15 illustrates the bus transactions for a 4-word data cache block store. data 0 data write data data eod data 3 data 2 data 1 addr 812 611 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd eok * pvalid * pmaster * figure 6.3.15 processor block write request with d data rate figure 6.3.16 illustrates a write request which is cancelled by the deassertion of eok eok eok eok * during the address cycle of the second write, and which is retried when eok eok eok eok * is asserted again. data 0 write write write eod eod eod data 1 data 1 addr 1 addr 1 addr 0 812 611 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd eok * pvalid * pmaster * figure 6.3.16 processor single write request followed by a cancelled and retried write request
chapter 6 tx4955a system interface 6-48 6.3.9 processor read request a processor read request is issued by the following: ? driving a read command on the syscmd bus ? driving a read address on the sysad bus ? asserting pvalid pvalid pvalid pvalid * only one processor read request may be pending at a time. the processor must wait for an external read response before starting a subsequent read. the processor moves to slave state after the issue cycle of the read request, by deasserting the pmaster pmaster pmaster pmaster * signal. an external agent may then return the requested data through a read response. the external agent, which is now bus master, may issue any number of writes before sending the read response data. an example of a processor read request and an uncompelled change to slave state occurring as the read request is issued is illustrated in figure 6.3.17. read addr 812 611 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd eok * pvalid * pmaster * figure 6.3.17 processor read request the tx4955a support the read time out function. this function is when the retern data wait but the time out counter. see chapter 6.3.20 mode register of system interface (g2sconfig). 6.3.10 external write request external write requests are similar to a processor single write except that the signal evalid is asserted instead of the signal pvalid pvalid pvalid pvalid * . an external write request consists of the following: ? an external agent driving a write command on the syscmd bus and a write address on the sysad bus ? asserting evalid evalid evalid evalid * for one cycle ? driving a data identifier on the syscmd bus and data on the sysad bus ? asserting evalid evalid evalid evalid * for one cycle. the data identifier associated with the data cycle must contain a last data cycle indication. note that the external agent must gain and maintain bus mastership during these transactions (see ereq ereq ereq ereq * in the timing summary, earlier in this chapter). an external write request example with the processor initially in master state is illustrated in figure 6.3.18.
chapter 6 tx4955a system interface 6-49 eod write data addr 812 611 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd ereq * evalid * pvalid * pmaster * figure 6.3.18 external write request an example of a read response for a processor single word read request that is interrupted by an external agent write request is illustrated in figure 6.3.22. external writes can not occur in the middle of a data response block; they can, however, occur before the first data response of the data block or after the last eod response, but it can not occur between them. note: the only writable resources are processor interrupts. an external write to any address is treated as a write to the processor interrupts.
chapter 6 tx4955a system interface 6-50 6.3.11 external read response an external agent returns data to the processor in response to a processor read request by waiting for the processor to move to slave state. the external agent then returns the data through either a single data cycle or a series of data cycles sufficient to transmit the requested data. after the last data cycle is issued, the read response is complete and the processor becomes master (assuming ereq ereq ereq ereq * was not asserted). if, at the end of the read response cycles, ereq ereq ereq ereq * has been asserted, the processor remains in slave state until the external agent relinquishes the bus. when the processor is in slave state and needs access to the sysad bus, it waits until ereq ereq ereq ereq * is deasserted. the data identifier associated with a data cycle may indicate that the data transmitted during that cycle is erroneous; however, an external agent must return a block of data of the correct size regardless of this erroneous data cycle indication. if a read response includes one or more erroneous data cycles, the processor takes a bus error. read response data must only be delivered to the processor when a processor read request is pending. the state of the processor is undefined if a read response is presented to it when no processor read is pending. an example of a processor single read request followed by a read response is illustrated in figure 6.3.19. eod data read addr 812 6 11 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd eok evalid pvalid pmaster figure 6.3.19 single read request followed by read response a read response example for a processor block read with the system interface already in slave state is illustrated in figure 6.3.20. data 3 data 2 data 1 data 0 eod data data data 812 6 11 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd evalid * pvalid * pmaster * figure 6.3.20 block read response, system interface already in slave state
chapter 6 tx4955a system interface 6-51 a read response example for a processor single read request followed by an external agent write request is illustrated in figure 6.3.21. write eod eod data data read addr addr 812 6 11 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd eok * ereq * evalid * pvalid * pmaster * figure 6.3.21 single read request followed by external write request (external agent keeps bus) an example of a read response for a processor single word read request that is interrupted by an external agent write request is illustrated in figure 6.3.22. cycle 5 is the data for the external write request in cycle 4. cycle 7 is the read response data. write eod eod data data read addr addr 812 6 11 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd eok * evalid * pvalid * pmaster * figure 6.3.22 external write followed by external read response, system interface in slave state
chapter 6 tx4955a system interface 6-52 6.3.12 flow control eok eok eok eok * may be used by an external agent to control the flow of processor read and write requests; while eok eok eok eok * is deasserted the processor will repeat the current address cycle until an external agent signals it is ready, by asserting eok eok eok eok * . there is a one cycle delay from the assertion of eok eok eok eok * to the state in which the read/write command becomes valid. eok eok eok eok * must be asserted for two consecutive cycles for the command issue completion. examples of eok eok eok eok * use are given in figure 6.3.23 and 6.3.24. read addr 812 6 11 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd eok * pvalid * pmaster * figure 6.3.23 delayed processor read request eod data eod data write write addr1 addr0 812 6 11 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd eok * pvalid * pmaster * figure 6.3.24 two processor write requests, second write delayed
chapter 6 tx4955a system interface 6-53 6.3.13 data rate control the system interface supports a maximum data rate of one word per cycle, and an external agent may deliver data to the processor at this maximum data rate. the rate at which data is delivered to the processor can be controlled by the external agent by driving data and asserting evalid evalid evalid evalid * only when it wants data to be available. the processor interprets cycles as valid data cycles when evalid evalid evalid evalid * is asserted and the syscmd bus contains a data identifier. the processor continues to accept data until the end of data (eod) indicator is received. the rate at which the processor transmits data to an external agent is programmed in the wbrate field in g2s config register. data patterns are specified using the letters d d d d and x x x x (d d d d indicates a data cycle and x x x x indicates an unused, or idle, cycle). a data pattern is specified as a sequence of data and unused cycles that will be repeated to provide the appropriate number of data cycles for a given transfer. for example, a data pattern of ddxx ddxx ddxx ddxx indicates a data rate of two words every four cycles. tx4955a supports two data rates, d d d d and dxx dxx dxx dxx. during a cycle indicated by an x x x x, the processor continues to hold the same data as the previous cycle. a processor block write request for two words with dxx pattern is illustrated in figure 6.3.25; this transaction results from a store doubleword instruction. eod data data 1 data 1 data 1 data 0 data 0 data 0 write addr 812 6 11 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd eok * pvalid * pmaster * figure 6.3.25 processor block write request with dxx data rate
chapter 6 tx4955a system interface 6-54 6.3.14 consecutive sysad bus transactions the following figures (figure 6.3.26 to 6.3.29) illustrate the minimum cycles required between consecutive bus transactions. eod eod data data data 1 data 0 write read addr1 addr0 8 6 11 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd evalid * eok * pvalid * pmaster * figure 6.3.26 processor single word read followed by block write request eod eod eod data addr2 data addr1 data write write write addr0 812 6 11 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd eok * pvalid * pmaster * figure 6.3.27 consecutive processor single word write requests with d data rate eod eod data data data data data addr1 data write write addr0 812 6 11 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd eok * pvalid * pmaster * figure 6.3.28 consecutive processor single word write requests with dxx data rate
chapter 6 tx4955a system interface 6-55 eod eod eod data data data write write write addr addr1 addr0 8 6 11 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd ereq * evalid * eok * pvalid * pmaster * figure 6.3.29 consecutive processor write requests followed by external write request block read maximum rate maximum block reads can occur with the following data rate: axd...dxaxd...d (1 cycle between d and a) where a a a a is the address, d d d d is data (four words, or dddd, in the data cache miss, and 8 words, or dddddddd, in an instruction cache miss), and x x x x is an idle cycle. back-to-back instruction cache misses with a pclock to sclock ratio of 2:1, back-to-back instruction cache misses can be refilled with the following data rate: axddddddddxxxaxdddddddd (3 cycles between d and a) that is, the address is followed by an idle cycle, the instruction is executed, three idle cycles occur, followed by the next address. this pattern is valid for the case in which two sequential instructions miss in the instruction cache, each instruction residing on a different cache line. running completely in uncached space (every instruction is uncached and a cache miss) results in a similar data pattern: axdxxxaxd (3 cycles between d and a) back-to-back uncached loads with a pclock to sclock ratio of 2:1, back-to-back uncached doubleword loads have the following data rate: axddxxxaxdd (3 cycles between d and a) that is, the address is followed by an idle cycle, a doubleword of data, three idle cycles, and the next address. back-to-back uncached word loads have the following data rate: axdxxxaxd (3 cycles between d and a)
chapter 6 tx4955a system interface 6-56 6.3.15 starvation and deadlock avoidance. careful use of the ereq ereq ereq ereq * signal allows a system to avoid starvation and deadlock situations. whenever an external agent needs the bus, it can request the bus by asserting ereq ereq ereq ereq * . the external agent is guaranteed to gain mastership of the bus after accepting at most one read/write request from the processor. if the external agent also deasserts eok eok eok eok * , it is guaranteed to gain mastership of the bus without accepting any read/write request from the processor. the external agent can allow the processor to gain bus mastership, perform one read/write request and then relinquish mastership by the following sequence of actions: 1. deassert ereq ereq ereq ereq * 2. assert ereq ereq ereq ereq * 3. arbitrate for the bus while asserting eok eok eok eok * the minimum deassertion of ereq ereq ereq ereq * can be one cycle in length. shows an external agent relinquishing the bus to allow a single read/write request from the processor. the external agent must be ready to accept this request by keeping eok eok eok eok * asserted, otherwise the read/write request is held off or killed and the processor relinquishes bus mastership without extending a request. this could lead to starvation of the processor. eod data data 0 data 1 write addr 8 611 10 9 7 5 4 3 2 1 sysad scycle sclock syscmd pvalid * eok * ereq * pmaster * figure 6.3.30 external agent gives up bus for one processor request 6.3.16 discarding and re-executing read command figure 6.3.31 illustrates how a processor single read request is discarded and reexecuted. the following sequence describes the protocol. ? because the eok eok eok eok * signal is low in cycle 5, the processor tries to issue an address (cycle 6). ? if the eok eok eok eok * signal is high at this point, the processor discards this read request and enters the slave status in the next cycle. ? because the ereq ereq ereq ereq * signal is inactive, the processor returns to the master status again and reissues a read request. because the eok eok eok eok * signal is low in both the cycles 7 and 8, the issuance cycle of the read request is determined. ? the external agent outputs data at the requsted address.
chapter 6 tx4955a system interface 6-57 eod data hi-z hi-z hi-z addr read 8 611 10 9 7 5 4 3 2 1 sysad(31:0) scycle sclock syscmd(4:0) evalid * pvalid * eok * ereq * pmaster * 12 data addr hi-z hi-z hi-z figure 6.3.31 discarding and re-executing processor single read request 6.3.17 multiple drivers on the sysad bus in most applications, the sysad bus is a point-to-point connection between the processor and a bidirectional, registered transceiver located in an external agent. in this application, the sysad bus has two possible drivers: the processor and the external agent. however, an application may add additional drivers and receivers to the sysad bus, allowing transmissions over the sysad bus that bypass the processor. to accomplish this, the external agent(s) must coordinate its use of the sysad bus by using arbitration handshake signals such as ereq ereq ereq ereq * and pmaster pmaster pmaster pmaster * . to implement an independent transmission on the sysad bus that does not involve the processor, the system executes the following sequence of actions: 1. the external agent(s) requests the sysad bus by asserting ereq ereq ereq ereq * . 2. the processor releases the system interface to slave state. 3. the external agent(s) allows independent transmission over the sysad bus, making certain the evalid evalid evalid evalid * input to the processor is not asserted while the transmission occurs. 4. when the transmission is complete, the external agent(s) deasserts ereq ereq ereq ereq * to return the system interface to master state. to implement multiple drivers, separate valid valid valid valid lines are required for non-processor chips to communicate.
chapter 6 tx4955a system interface 6-58 6.3.18 signal codes system interface commands and data identifiers are encoded in five bits on the syscmd bus and transmitted between the processor and external agent during address and data cycles. ? when syscmd (4) syscmd (4) syscmd (4) syscmd (4) is a 0, the current cycle is an address cycle and syscmd (3:0) syscmd (3:0) syscmd (3:0) syscmd (3:0) contains a command. ? when syscmd (4) syscmd (4) syscmd (4) syscmd (4) is a 1, the current cycle is a data cycle and syscmd (3:0) syscmd (3:0) syscmd (3:0) syscmd (3:0) identifies data. for commands and data identifiers associated with external requests, all bits and fields have a value or a suggested value. for system interface commands and data identifiers associated with processor requests, reserved bits and reserved fields in the command or data identifier are undefined, except where noted. for all system interface commands, the syscmd bus specifies the system interface request type. the encoding of syscmd (4) syscmd (4) syscmd (4) syscmd (4) for system interface commands is table 6.3.3. table 6.3.3 encoding of system interface commands in syscmd (4) syscmd(4) command 0 address cycle 1 data cycle for address requests, the remainder of the syscmd bus specifies the attributes of the address request, as follows: ? syscmd (3) syscmd (3) syscmd (3) syscmd (3) encodes the address request type. ? syscmd (2:0) syscmd (2:0) syscmd (2:0) syscmd (2:0) indicates the size of the address requests. the encoding of syscmd (3:2) for address requests is shown in table 6.3.4. table 6.3.4 encoding of syscmd(3) and syscmd(2) for address cycle syscmd (3) command syscmd (2) request size 0 read request 0 single data 1 write request 1 block data note:tx4955a support only external single data write request. the encoding of syscmd (1:0) syscmd (1:0) syscmd (1:0) syscmd (1:0) for block or single address requests is shown in table 6.3.5 and 6.3.6, respectively. table 6.3.5 encoding of syscmd (1:0) for block address requests syscmd (1:0) block size 0 reserved. 1 four words(only data cache). 2 eight worde. 3 reserved.
chapter 6 tx4955a system interface 6-59 table 6.3.6 encoding of syscmd (1:0) for single address requests syscmd (1:0) data size. 0 one byte valid (byte) 1 two bytes valid (halfword). 2 three bytes valid (tribyte). 3 four bytes valid (single word) the encoding of syscmd (3:0) for processor data identifiers is described in table 6.3.7. the encoding of syscmd (3:0) for external data identifiers is illustrated in table 6.3.8. table 6.3.7 encoding of syscmd(3:0) for processor data identifiers syscmd (3) last data element indication 0 last data element 1 not the last data element syscmd (2) reserved syscmd (1) reserved for : good data indication processor drives 0 (data is error free) syscmd (0) reserved for : data checking enable processor drives 1 (disable data checking) table 6.3.8 encoding of syscmd(3:0) for external data identifiers syscmd (3) last data element indication 0 last data element 1 not the last data element syscmd (2) response data indication 0 data is response data 1 data is not response data syscmd (1) reserved for : good data indication 0 data is error free 1 data is erroneous syscmd (0) reserved for : data checking enable processor ignores this field (suggested drive of 1, disable data checking) note: external read requests for processor resources are not supported in the tx4955a processor.
chapter 6 tx4955a system interface 6-60 6.3.19 physical addresses physical addresses are driven on all 32 bits (bits 31 through 0) of the sysad bus during address cycles. addresses associated with single read and write requests are aligned for the size of the data element; specifically, for single word requests, the low order two bits of the address are zero, for halfword requests, the low order bit of the address is zero. for byte and tribyte requests, the address provided is a byte address. external agents returning read response data must support subblock ordering. addresses associated with block read requests are aligned to the word of the desired data. the order in which data is returned in response to a processor block read request is: ? the word containing the addressed data word is returned first ? the remaining word(s) in the block are returned next, sequentially block writes are always block aligned 6.3.20 mode register of system interface (g2sconfig) the mode register of system interface (g2scofig) is a read/write register. this register extend from tx4300. this register is only word-access. table 6.3.9 g2sconfig address field desctiption 0xf_ff10_0000 g2sconfig mode register of system interface 31 20 19 4 3 2 1 0 reserved=0 toutval tout enable reserved=0 burst8 wbrate figure 6.3.32 g2sconfig register format table 6.3.10 g2sconfig register formats (mode43 * = 0) bit field description coldreset read/write 31 ~ 20 ? reserved undefined read 19 ~ 4 toutval set data of read time out counter 0xffff read/write 3 toutenable enable bit of read time out counter 0: disable 1: enable 0 read/write 2 ? reserved undefined 1 burst8 data formats at 8-word burst write 0: double burst mode 4 words 2 1: single burst mode 8 words 0 read/write 0 wbrate set bit of data out formats 0: every cycle data out 1: 4-word data out per 12 cycles 0 read/write
chapter 6 tx4955a system interface 6-61 6.3.21 read time out counter (mode43 * = 0) this counter is used to detect time-out when data is not returned during read. the counter normally is set by loading the g2sconfig register?s toutval as its initial value. when one of the conditions below is met, the counter counts down one every bus cycle and upon reaching the terminal count of 0, generates a time-out signal and asserts a bus error signal for one cycle before entering an idle state. if none of the following conditions is met, the value of toutval is reloaded into the counter. ? toutenable = 1 ? waiting for data note1: for tx4955a, read time out counter does not work when mode43 * = 1. when the read time out counter functions is used, the value of the more than which added 24 the twice of the wait cycle of the main memory must be set to the toutval field. note2: read time out error occurs by writing 0x0 into toutval while read time out counter is disable. so toutval must be set except for 0x0.
chapter 6 tx4955a system interface 6-62
chapter 7 jtag interface 7-1 chapter 7. jtag interface the tx4955a processor provides a boundary-scan interface that is compatible with joint test action group (jtag) specifications, using the industry-standard jtag protocol (ieee standard 1149.1/d6). this chapter describes that interface, including descriptions of boundary scanning, the pins and signals used by the interface, and the test access port (tap). 7.1 what boundary scanning is with the evolution of ever-denser integrated circuits (ics), surface-mounted devices, double-sided component mounting on printed-circuit boards (pcbs), and buried vias, in-circuit tests that depend upon making physical contact with internal board and chip connections have become more and more difficult to use. the greater complexity of ics has also meant that tests to fully exercise these chips have become much larger and more difficult to write. one solution to this difficulty has been the development of boundary-scan circuits. a boundary-scan circuit is a series of shift register cells placed between each pin and the internal circuitry of the ic to which the pin is connected, as shown in figure 7.1.1. normally, these boundary-scan cells are bypassed; when the ic enters test mode, however, the scan cells can be directed by the test program to pass data along the shift register path and perform various diagnostic tests. to accomplish this, the tests use the four signals described in the next section: jtdi jtdi jtdi jtdi, jtdo jtdo jtdo jtdo, jtms jtms jtms jtms, jtck jtck jtck jtck, and trst , and trst , and trst , and trst * . figure 7.1.1 jtag boundary-scan cells integrated circuit c package pin boundary-scan cells
chapter 7 jtag interface 7-2 7.2 signal summary the jtag interface signals are listed below and shown in figure 7.2.1. ? jtdi jtag serial data in ? jtdo jtag serial data out ? jtms jtag test mode select ? jtck jtag serial clock input ? trst jtag test reset input figure 7.2.1 jtag interface signals and registers the jtag boundary-scan mechanism (referred to in this chapter as jtag mechanism ) allows testing of the connections between the processor, the printed circuit board to which it is attached, and the other components on the circuit board. the jtag mechanism does not provide any capability for testing the processor itself. 70 instruction register tap controller 0 bypass register 0 86 boundary-scan register 31 0 device identification register jtdi pin jtd0 pin jtms pin jtck pin trst * pin
chapter 7 jtag interface 7-3 7.3 jtag controller and registers the processor contains the following jtag controller and registers: ? instruction register ? boundary-scan register ? bypass register ? id code register ? test access port (tap) controller the processor executes the standard jtag extest operation associated with external test functionality testing. the basic operation of jtag is for the tap controller state machine to monitor the jtms input signal. when it occurs, the tap controller determines the test functionality to be implemented. this includes either loading the jtag instruction register (ir), or beginning a serial data scan through a data register (dr), listed in table 8-1. as the data is scanned in, the state of the jtms pin signals each new data word, and indicates the end of the data stream. the data register to be selected is determined by the contents of the instruction register. 7.3.1 instruction register the jtag instruction register includes eight shift register-based cells; this register is used to select the test to be performed and/or the test data register to be accessed. as listed in table 7.3.1, this encoding selects either the boundary-scan register or the bypass register or device identification register. table 7.3.1 jtag instruction register bit encoding instruction code (msb lsb) instruction selected data register 00000000 extest boundary scan register 00000001 sample/preload boundary scan register 00000010 reserved reserved 00000011 idcode device identification register 00000100 ~ 01111111 reserved reserved 10000000 ~ 11111110 debug support unit please refer dsu section 11111111 bypass bypass register figure 7.3.1 shows the format of the instruction register 76543210 msb lsb figure 7.3.1 instruction register the instruction code is shifted out to the instruction register from the lsb. figure 7.3.2 instruction register shift direction lsb jtdo jtdi msb
chapter 7 jtag interface 7-4 7.3.2 bypass register the bypass register is 1 bit wide. when the tap controller is in the shift-dr (bypass) state, the data on the jtdi pin is shifted into the bypass register, and the bypass register output shifts to the jtdo output pin. in essence, the bypass register is a short-circuit which allows bypassing of board-level devices, in the serial boundary-scan chain, which are not required for a specific test. the logical location of the bypass register in the boundary-scan chain is shown in figure 7.3.3. use of the bypass register speeds up access to boundary-scan registers in those ics that remain active in the board-level test datapath. figure 7.3.3 bypass register operation jtdo board input ic package board jtdi bypass register boundary-scan register pad cell board output jtdi jtdi jtdo jtdo jtdo jtdi jtdo jtdi
chapter 7 jtag interface 7-5 7.3.3 boundary-scan register the boundary scan register includes all of the inputs and outputs of the tx4955a processor, except some clock and phase lock loop signals. the pins of the tx4955a chip can be configured to drive any arbitrary pattern by scanning into the boundary scan register from the shift-dr state. incoming data to the processor is examined by shifting while in the capture-dr state with the boundary scan register enabled. the boundary-scan register is a single, 87-bit-wide, shift register-based path containing cells connected to all input and output pads on the tx4955a processor. figure 7.3.4 shows the boundary-scan register. 86 10 see table 7.3.2 sysen1 figure 7.3.4 format of the boundary-scan register the most-significant bit, sysen (bit3 to bit0), are the jtag output enable bit for all outputs of the processor. output is enabled when those bit are set to 1 (default state). the remaining 83 bits correspond to 83 signal pads of the processor. at the end of this chapter, table 7.3.2 lists the scan order of these 89 scan bits, starting from jtdi jtdi jtdi jtdi and ending with jtdo jtdo jtdo jtdo. the jtdi input is loaded to the lsb of the boundary scan register. the msb of the boundary scan register is retrieved from the jtdo output. 7.3.4 device identification register the device identification register is a 32-bit shift register. it is used to read serially from the ic the identification code indicating the ic manufacturer, part number, and version. the following shows the device identification register structure. 31 28 27 12 11 1 0 version product number manufacturer identification code 1 4 bits 16 bits 11 bits figure 7.3.5 device identification register the tx4955a device identification code is 0x00017031. the device identification code is shifted out starting from the lsb. figure 7.3.6 devide identification register shift direction lsb jtdo msb
chapter 7 jtag interface 7-6 7.3.5 test access port (tap) the test access port (tap) consists of the five signal pins: trst trst trst trst * jtdi jtdi jtdi jtdi, jtdo jtdo jtdo jtdo, jtms jtms jtms jtms, and jtck jtck jtck jtck. serial test data and instructions are communicated over these five signal pins, along with control of the test to be executed. as figure 7.3.7 shows, data is serially scanned into one of the four registers ( instruction register, bypass register, device identification register, or the boundary-scan register) from the jtdi jtdi jtdi jtdi pin, or it is scanned from one of these four registers onto the jtdo jtdo jtdo jtdo pin. the jtms jtms jtms jtms input controls the state transitions of the main tap controller state machine. the jtck jtck jtck jtck input is a dedicated test clock that allows serial jtag data to be shifted synchronously, independent of any chip-specific or system clocks. figure 7.3.7 jtag test access port data on the jtdi jtdi jtdi jtdi and jtms jtms jtms jtms pins is sampled on the rising edge of the jtck jtck jtck jtck input clock signal. data on the jtdo jtdo jtdo jtdo pin changes on the falling edge of the jtck jtck jtck jtck clock signal. 7.3.6 tap controller the processor implements the 16-state tap controller as defined in the ieee jtac specification. 7.3.7 controller reset the tap controller state machine can be put into reset state the following: ? assertion of the trst trst trst trst * signal (low) resets the tap controller. ? keeping the jtms jtms jtms jtms input signal asserted through five consecutive rising edges of jtck jtck jtck jtck input. in either case, keeping jtms jtms jtms jtms asserted maintains the reset state. jtck data scanned out serially jtd0 sampled on falling edge of jtck jtms and jtdi sampled on rising edge of jtck data scanned in serially jtdi pin jtms pin jtdo pin 0 0 7 instruction register bypass register 86 boundary-scan registe 0 0 0 7 instruction register bypass register 86 boundary-scan register 031 device identification register 0
chapter 7 jtag interface 7-7 7.3.8 tap controller the state transition diagram of the tap controller is shown in figure 7.3.8. each arrow between states is labeled with a 1 or 0, indicating the logic value of jtms that must be set up before the rising edge of jtck to cause the transition. test-logic-reset 1 0 0 1 0 1 run-test/idle select-dr-scan 1 1 capture-dr 0 shift-dr 1 exit 1-dr 0 pause-dr 1 exit 2-dr 1 update-dr 0 1 0 0 1 select-ir-scan capture-ir 0 shift-ir 1 exit 1-ir 0 pause-ir 1 exit 2-ir 1 update-ir 0 1 1 00 1 0 0 0 figure 7.3.8 tap controller state diagram the following paragraphs describe each of the controller state. the left vertical column in figure 7.3.8 is the data column, and the right vertical column is the instruction column. the data column and instruction column reference data register (dr) and instruction register (ir), respectively.
chapter 7 jtag interface 7-8 ? test-logic-reset when the tap controller is in the reset state, the value 0x3 is loaded into the parallel output latch, selecting the device identification register as default. the three most significant bits of the boundary-scan register are cleared to 0, disabling the outputs. the controller remains in this state while jtms is high. if jtms is held low while the controller is in this state, then the controller moves to the run-test/idle state. ? run-test/idle in the run-test/idle state, the ic is put in a test mode only when certain instructions such as a built-in self test (bist) instruction are present. for instructions that do not cause any activities in this state, all test data registers selected by the current instruction retain their previous states. the controller remains in this state while jtms is held low. when jtms is high, the controller moves to the select-dr-scan state. ? select-dr-scan this is a temporary controller state. here, the ic does not execute any specific functions. if jtms is held low when the controller is in this state, then the controller moves to the capture-dr state. if jtms is held high, the controller moves to the select-ir-scan state in the instruction column. ? select-ir-scan this is a temporary controller state. here, the ic does not execute any specific functions. if jtms is held low when the controller is in this state, then the controller moves to the capture-ir state. if jtms is held high, the controller returns to the test-logic-reset state. ? capture-dr in this controller state, if the test data register selected by the current instruction on the rising edge of jtck has parallel inputs, then data can be parallel-loaded into the shift portion of the data register. if the test data register does not have parallel inputs, or if data need not be loaded into the selected data register, then the data register retains its previous state. if jtms is held low while the controller is in this state, the controller moves to the shift-dr state. if jtms is held high, the controller moves to the exit1-dr state. ? shift-dr in this controller state, the test data register connected between jtdi and jtdo shifts data one stage forward towards its serial output. when the controller is in this state, then it remains in the shift-dr state if jtms is held low, or moves to the exit1-dr state if jtms is held high.
chapter 7 jtag interface 7-9 ? exit 1-dr this is a temporary controller state. if jtms is held low when the controller is in this state, then the controller moves to the pause-dr state. if jtms is held high, the controller moves to the update-dr state. ? pause-dr this state allows the shifting of the data register selected by the instruction register to be temporarily suspended. both the instruction register and the data register retain their current states. when the controller is in this state, then it remains in the pause-dr state if jtms is held low, or moves to the exit2-dr state if jtms is held high. ? exit 2-dr this is a temporary controller state. when the controller is in this state, then it returns to the shift-dr state if jtms is held low, or moves on to the update-dr state if jtms is held high. ? update-dr in this state, data is latched, on the falling edge of jtck, onto the parallel outputs of the data registers from the shift register path. the data held at the parallel output does not change while data is shifted in the associated shift register path. when the controller is in this state, it moves to either the run-test/idle state if jtms is held low, or the select-dr-scan state if jtms is held high. ? capture-ir in this state, data is parallel-loaded into the instruction register. the two least significant bits are assigned the values ?01?. the higher-order bits of the instruction register can receive any design specific values. the capture-ir state is used for testing the instruction register. faults in the instruction register, if any exists, may be detected by shifting out the data loaded in it. when the controller is in this state, it moves to either the shift-ir state if jtms is low, or the exit1-ir state if jtms is high. ? shift-ir in this state, the instruction register is connected between jtdi and jtdo and shifts the captured data toward its serial output on the rising edge of jtck. when the controller is in this state, it remains in the shift-ir state if jtms is low, or moves to the exit1-ir state if jtms is high.
chapter 7 jtag interface 7-10 ? exit 1-ir this is a temporary controller state. when the controller is in this state, then it moves to either the pause-ir state if jtms is held low, or the update-ir state if jtms is held high. ? pause-ir this state allows the shifting of the instruction register to be temporarily suspended. both the instruction register and the data register retain their current states. when the controller is in this state, it remains in the pause-ir state if jtms is held low, or moves to the exit2-ir state if jtms is held high. ? exit 2-ir this is a temporary controller state. when the controller is in this state, it moves to either the shift-ir state if jtms is held low, or the update-ir state if jtms is held high. ? update-ir this state allows the instruction previously shifted into the instruction register to be output in parallel on the rising edge of jtck. then it becomes the current instruction, setting a new operational mode. when the controller is in this state, it moves to either the run-test/idle state if jtms is low, or the select-dr-scan state if jtms is high. tables 7.3.2 shows the boundary scan order of the processor signals. table 7.3.2 tx4955a jtag boundary-scan ordering [jtdi] 1: sysen1 2: sysen2 3: sysen3 4: sysen4 5: bufsel1 6: sysad4 7: sysad5 8: sysad6 9: sysad7 10: sysad8 11: sysad9 12: sysad10 13: sysad11 14: sysad12 15: sysad13 16: sysad14 17: sysad15 18: bufsel0 19: pcst3 20: pcst2 21: pcst1 22: pcst0 23: rdrdy * 24: wrrdy * 25: validin * 26: validout * 27: release * 28: pllres * 29: tintdis 30: syscmd0 31: syscmd1 32: syscmd2 33: syscmd3 34: syscmd4 35: syscmd5 36: syscmd6 37: syscmd7 38: syscmd8 39: syscmdp 40: haltdoze 41: int0 * 42: int1 * 43: int2 * 44: int3 * 45: int4 * 46: int5 * 47: tpc3 48: tpc2 49: tpc1 50: dclk 51: nmi * 52: extrqst * 53: reset * 54: coldreset * 55: endian 56: sysad16 57: sysad17 58: sysad18 59: sysad19 60: sysad20 61: sysad21 62: sysad22 63: sysad23 64: sysad24 65: sysad25 66: sysad26 67: sysad27 68: mode43 * 69: divmode1 70: divmode0 71: sysad28 72: sysad29 73: sysad30 74: sysad31 75: sysadc2 76: sysadc3 77: sysadc0 78: sysadc1 79: sysad0 80: sysad1 81: sysad2 82: sysad3 83: pcst8 84: pcst7 85: pcst6 86: pcst5 87: pcst4 [jtdo]
chapter 7 jtag interface 7-11 7.4 instructions for jtag this section defines the instructions supplied and the operations that occur in response to those instructions. 7.4.1 the extest instruction this instruction is used for external interconnect test, and targets the boundary scan register between jtdi and jtdo. the extest instruction permits bsr cells at output pins to shift out test patterns in the update-dr state and those at input pins to capture test results in the capture-dr state. typically, before extest is executed, the initialization pattern is first shifted into the boundary scan register using the sample/preload instruction. in the update-dr state, the boundary scan register loaded with the initialization pattern causes known data to be driven immediately from the ic onto its external interconnects. this eliminates the possibility that bus conflicts damage the ic outputs. the flow of data through the boundary scan register while the extest instruction is selected is shown in figure 7.4.1, which follows: figure 7.4.1 test data flow while the extest instruction is selected the following steps describe the basic test algorithm of an external interconnect test. 1. initialize the tap controller to the test-logic-reset state. 2. load the instruction register with sample/preload. this causes the boundary scan register to be connected between jtdi and jtdo. 3. initialize the boundary scan register by shifting in determinate data. 4. then, load the initial test data into the boundary scan register. 5. load the instruction register with extest. 6. capture the data applied to the input pin into the boundary scan register. 7. shift out the captured data while simultaneously shifting in the next test pattern. 8. read out the data in the boundary scan register onto the output pin. steps 6 to 8 are repeated for each test pattern. core logic output jtdo input jtdi boundary scan path
chapter 7 jtag interface 7-12 7.4.2 the sample/preload instruction this instruction targets the boundary scan register between jtdi and jtdo. as the instruction's name implies, two functions are performed through use of the sample/ preload instruction. ? sample allows the input and output pads of an ic to be monitored. while it does so, it does not disconnect the system logic from the ic pins. the sample function occurs in the capture-dr controller state. an example application of sample is to take a snapshot of the activity of the ic's i/o pins so as to verify the interaction between ics during normal functional operation. the flow of data for the sample phase of the sample/preload instruction is shown in figure 7.4.2. figure 7.4.2 test data flow while sample is selected ? preload allows the boundary scan register to be initialized before another instruction is selected. for example, prior to selection of the extest instruction, initialization data is shifted into the boundary scan register using preload as described in the previous subsection. preload permits shifting of the boundary scan register without interfering with the normal operation of the system logic. the flow of data for the preload phase of the sample/preload instruction is shown in figure 7.4.3. figure 7.4.3 test data flow while preload is selected core logic output jtdo input jtdi boundary scan path output jtdo input jtdi boundary scan path core logic
chapter 7 jtag interface 7-13 7.4.3 the bypass instruction this instruction targets the bypass register between jtdi and jtdo. the bypass register provides a minimum length serial path through the ic (or between jtdi and jtdo) when the ic is not required for the current test. the bypass instruction does not cause interference to the normal operation of the on-chip system logic. the flow of data through the bypass register while the bypass instruction is selected is shown in figure 7.4.4. figure 7.4.4 test data flow while the bypass instruction is selected 7.4.4 the idcode instruction this instruction targets the device identification register between jtdi and jtdo to identify manufacturer identity, part number, and version number for the part. jtdo jtdi bypass register 1-bit
chapter 7 jtag interface 7-14 7.5 note this section discribes details of jtag boundary-scan operation that are specific to the processor. ? the masterclock masterclock masterclock masterclock, and pllcap pllcap pllcap pllcap signal pads do not supposrt jtag. ? when performing a jtag operation, be sure to run the masterclock masterclock masterclock masterclock before and after a reset operation to properly release the processor reset. ? reset for jtag c jtag circuit is initialized by trst trst trst trst * assertion. and then deassert trst trst trst trst * . at input to jtms jtms jtms jtms = 1 and asserted for more 5 jtck cycles.
chapter 8 tx4955a processor interrupts 8-1 chapter 8. tx4955a processor interrupts four types of interrupt are available on the tx4955a. these are: ? one non-maskable interrupt, nmi ? six external interrupts ? two software interrupts ? one timer interrupt these are described in this chapter. 8.1 nonmaskable interrupt the non-maskable interrupt is signaled by asserting the nmi nmi nmi nmi * pin (low), forcing the processor to branch to the reset exception vector. this pin is latched into an internal register by the rising edge of sclock sclock sclock sclock, as shown in figure 8.4.1. an nmi can also be set by an external write through the sysad sysad sysad sysad bus. on the data cycle, sysad (22) sysad (22) sysad (22) sysad (22) acts as the write enable for sysad (6) sysad (6) sysad (6) sysad (6), which is the value to be written as the interrupt. nmi only takes effect when the processor pipeline is running. thus nmi can be used to recover the processor from a software hang (for example, in an infinite loop) but cannot be used to recover the processor from a hardware hang (for example, no read response from an external agent). nmi cannot cause drive contention on the sysad sysad sysad sysad bus and no reset of external agents is required. this interrupt cannot be masked. the nmi nmi nmi nmi * pin is latched by the rising edge of sclock sclock sclock sclock, however the nmi exception occurs in response to the falling edge of the nmi nmi nmi nmi * signal, and is not level-sensitive. figure 8.4.1 shows the internal derivation of the nmi nmi nmi nmi signal. the nmi nmi nmi nmi * pin is latched into an internal register by the rising edge of sclock sclock sclock sclock. bit 6 of the interrupt register is then ored with the inverted value of nmi nmi nmi nmi * to form the nonmaskable interrupt. 8.2 external interrupts external interrupts are set by asserting the external interrupt pins int int int int ( ( ( (5 5 5 5:0) :0) :0) :0) * . they also may be set by an external write through the sysad sysad sysad sysad bus. during the data cycle, sysad (2 sysad (2 sysad (2 sysad (21 1 1 1:16) :16) :16) :16) are the write enables for bits sysad ( sysad ( sysad ( sysad (5 5 5 5:0) :0) :0) :0), which are the values to be written as interrupts. these interrupts can be masked with the im , ie , and exl fields of the status register. note: int5 * is doubled as a timer interrupt. therefore either is selected with the external pin (tintdis). 8.3 software interrupt software interrupts use bits 1 and 0 of the interrupt pending, ip , field in the cause register. these may be written by software, but there is no hardware mechanism to set or clear these bits. these interrupts are maskable.
chapter 8 tx4955a processor interrupts 8-2 8.4 timer interrupt the timer interrupt signal is bit 15 of the cause register, which is bit 7 of the interrupt pending, ip , field. the timer interrupt is set whenever the value of the count register equals the value of the compare register. this interrupt is maskable through the im field of the status register. note: timer interrupt is doubled as a int5 * . there fore either is selected with the external pin (tintdis). note: interrupt register : please see chapter 6 external write request figure 8.4.1 tx4955a interrupt control circuit interrupt register software interrupt nmi tintdis cause resister (buffer) 6 sysad 5 4 3 2 1 0 22 21 20 19 18 17 16 0 1 2 3 4 5 6 ip0 ip1 ip2 ip3 ip4 ip5 ip6 8 9 10 11 12 13 14 int0 * int1 * int2 * int3 * int4 * int5 * nmi * ip7 15 timer interrupt h: int5 * l: timer l h
chapter 8 tx4955a processor interrupts 8-3 8.5 asserting interrupts external writes to the cpu are directed to various internal resources, based on an internal address map of the processor. an external write to any address writes to an architecturally transparent register called the interrupt register; this register is available for external write cycles, but not for external reads. during a data cycle, sysad (2 sysad (2 sysad (2 sysad (22 2 2 2:16) :16) :16) :16) are the write enables for the seven individual interrupt register bits and sysad ( sysad ( sysad ( sysad (5 5 5 5:0) :0) :0) :0) are the values to be written into these bits. this allows any subset of the interrupt register to be set or cleared with a single write request. figure 8.4.1 shows the mechanics of an external write to the interrupt register, along with the nonmaskable interrupt described earlier. figure shows how the tx4955a hardware interrupts are readable through the cause register. ? bits 4:0 of the interrupt register are bit-wise ored with the current value of the interrupt pins int int int int * [4:0] [4:0] [4:0] [4:0] and the result is directly readable as bits 14:10 of the cause register. ? bit5 of the interrupt register is ored with the current value of the interrupt pin int5 * . bit15 of cause register is selected this ored signal or timer interrupt by tintdis. ip (1:0) of the cause register, which are described in chapter 8 8.3, are software interrupts. there is no hardware mechanism for setting or clearing the software interrupts. figure 8.5.1 shows the masking of the tx4955a interrupt signals. ? cause register bits 15:8 (ip7-ip0) are and-ored with status register interrupt mask bits 15:8 (im7-im0) to mask individual interrupts. ? status register bit 0 is a global interrupt enable (ie). it is anded with the output of the and-or logic to produce the tx4955a interrupt signal. the exl bit in the status register also enables these interrupts. figure 8.5.1 masking of the tx4955a interrupts status register sr (0) status register sr (15:8) tx4955a interrupt cause register (15:8) and function and-or function ie 1 1 8 8 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 im4 im3 im2 im1 im0 im5 im6 im7 external interrupts software interrupts timer interrupts or int5 *
chapter 8 tx4955a processor interrupts 8-4
chapter 9 debug support unit 9-1 chapter 9. debug support unit 9.1 features 1. utilizes jtag interface compatible with ieee std. 1149.1. 2. processor access to external processor probe to execute from the external trace memory during debug exception and boot time. this is to eliminate system memory for debugging purpose. 3. supports dma access through jtag interface to internal processor bus to access internal registers, host system peripherals and system memory. 4. debug functions ? instruction address break ? data bus break ? processor bus break ? reset, nmi, interrupt mask 5. instructions for debug ? sdbbp, deret, ctc0, cfc0 6. cp0 registers for debug ? debug, depc, desave 9.2 ejtag interface this interface consists of two modes of operation a run time mode and real time mode. the run time mode provides functions such as processor run, stop, single step, and access to internal registers and system memory. the real time mode provides additional status pins used in conjunction with jtag pins for real time trace information. table 9.2.1 jtag interface pin name i / o function jtdi i jtag data input / debug interrupt input run-time mode: input serial data to jtag data/instruction registers. real-time mode: interrupt input to change the debug unit state from real-time mode to run-time mode. jtck i jtag clock input clock input for jtag. the jtdi and jtms data are latched on rising edges of this clock. jtdo/tpc(0) o jtag data output / trace pc output data is serially shifted out from this pin. / outputs a non-sequential program counter value synchronously with dclk. jtms i jtag command controls mainly the status transition of the tap controller state machine. when the serial input data is a jtag command, apply a high signal (= 1) to this pin. dclk o debug clock (1/3 cpu clock) clock output for a real-time debug system. timings of the serial monitor bus and pc trace interface signals all are defined by this debug clock dclk. this debug clock frequency is 1/3 that of pclock. pcst(8:0) o pc trace status outputs pc trace status information and serial monitor bus mode. tpc(3:1) note 1 o trace pc output outputs a non-sequential program counter value synchronously with dclk. trst * i test reset input reset input for a real-time debug system. when trst* is asserted (= 0), the debug support unit (dsu) is initialized. note1: leave tpc (3-1) pins open when not using them as pc trace outputs for debugging.
chapter 9 debug support unit 9-2 9.3 jtag interface standard jtag interface is used for on chip debugging during run time mode. the tx49 debug support unit has following registers. ? instruction register ? bypass register ? boundary-scan register ? device identification register ? implementation register ? jtag_data_register ? jtag_address_register ? jtag_control_register 9.4 processor access overview the core processor can access external processor probe for reading and writing to external monitor memory, registers and other external resources. in addition the processor can execute from the external monitor memory located from 0xf_ff20 0000 to 0xf_ff2f ffff when the probenb bit is set and the processor probe is turned on. any access to the monitor location from 0xf_ff20 0000 to 0xf_ff3f ffff are only allowed when the processor is in the debug mode (dm = 1). 9.5 instruction the instruction is a 8 bit field. instructions for the tx49 debug support unit are encoded between 0x80 and 0x9f and other codes are reserved for toshiba standard jtag instructions (includes extest, sample/preload and idcode) and so on. instructions are decoded as follows. figure 9.5.1 instruction hex value instruction description 0x00 extest boundary scan register 0x01 sample/preload boundary scan register 0x02 reserve reserve 0x03 idcode device identification register 0x83 ejtag_impcode select implementation register 0x88 jtag_address_ir select jtag_address register 0x89 jtag_data_ir select jtag_data register 0x8a jtag_control_ir select jtag_control register 0x8b jtag_all_ir select jtag_all register 0x90 pctrace pcirace instruction 0xff bypass select bypass register note: 0x80 0x9f the other code. please does not used. any unused instruction between 0x80 and 0x9f defaulted to bypass instruction.
chapter 9 debug support unit 9-3 9.6 debug unit 9.6.1 extended instructions ? sdbbp ? deret ? ctc0 ? cfc0 9.6.2 extended debug registers in cp0 ? debug register ? debug exception pc (depc) ? debug save 9.7 register map table 9.7.1 register map address mnemonic description 0xf ff30 0000 dcr debug control register 0xf ff30 0008 ibs instruction break status 0xf ff30 0010 dbs data break status 0xf ff30 0018 pbs processor break status 0xf ff30 0100 iba0 instruction break address 0 0xf ff30 0108 ibc0 instruction break control 0 0xf ff30 0110 ibm0 instruction break address mask 0 0xf ff30 0300 dba0 data break address 0 0xf ff30 0308 dbc0 data break control 0 0xf ff30 0310 dbm0 data break address mask 0 0xf ff30 0318 db0 data break value 0 0xf ff30 0600 pba0 processor bus break address 0 0xf ff30 0608 pbd0 processor bus break data 0 0xf ff30 0610 pbm0 processor bus break mask 0 0xf ff30 0618 pbc0 processor bus break control 0 9.8 processor bus break function this function is to monitor the interface to core and provide debug interruption or trace trigger for a given physical address and data.
chapter 9 debug support unit 9-4 9.9 debug exception three kinds of debug exception are supported. ? debug single step (dss bit) ? debug breakpoint exception (sdbbp instruction) ? jtag break exception (jtagbrk bit in jtag_control_register) note: during real time debugging, first two functions are disabled. 9.9.1 debug single step (dss) when the debug register dss bit is set, this exception has been raised each time one instruction is executed. 9.9.2 debug breakpoint exception (dbp) this exception is raised when sdbbp instruction is executed. 9.9.3 jtag break exception this exception is raised when jtag unit set the jtagbrk in jtag_control_register. 9.9.4 debug exception handling updates depc and debug register. registers other than depc and debug register retain their values. 9.9.5 branching to debug handler if the probenb bit in jtag_control_register[15] is set, the debug exception vector is located at pc: 0xffff ffff ff20 0200 if the probenb bit in jtag_conctrol_register[15] is cleared, the debug exception vector is located at pc: 0xffff ffff bfc0 0400 9.9.6 exception handling when in debug mode (dm bit is set) all interrupts including nmi are masked. when the nmi interrupt has occurred during debug mode, it is stored internally and the nmi interrupt is taken after debug handler is finished (dm is clear) 9.10 real time pc trace output in real time mode non-sequential program counter and trace information are outputted on tpc[3:0] and pcst[8:0] at 1/3 of the processor clock speed.
chapter 10 electrical characteristics 10-1 chapter 10. electrical characteristics esd precautions: for handling precautions, see section 1.1, electrostatic discharge (esd), in the chapter on general safety precautions and usage considerations. 10.1 electrical characteristics of tmpr4955af 10.1.1 absolute maximum ratings v ss = 0 v (gnd) parameter symbol ratings unit supply voltage (for i/o) vcciomax ? 0.5 3.9 v supply voltage (for internal) vccintmax ? 0.5 3.0 v input voltage ( * 1) v in ? 0.5 v cc io + 0.3 v storage temperature t stg ? 65 + 150 c note: the absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. ( * 1) vin min = ? 1.5 v for pulse width less than 10 ns. 10.1.2 recommended operating conditions v ss = 0 v (gnd) parameter symbol conditions min max unit supply voltage (for i/o) vccio 3.1 3.5 v supply voltage (for internal) vccint 1.4 1.6 v operating case temperature t c 0 + 70 c note: the recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. if the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified an and dc values etc.), malfunction may occur. thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to.
chapter 10 electrical characteristics 10-2 10.1.3 dc characteristics t c = 0 c to 70 c, vccint = 1.5 v 0.1 v, vccio = 3.3 v 0.2 v parameter symbol conditions min typ. max units output high voltage v oh vccio = 3.3 v, vss = 0 v i oh = ? 4 ma 2.4 v output low voltage v ol vccio = 3.3 v, vss = 0 v i ol = 4 ma 0.4 v input high voltage ( * 2) v ih 2.0 vccio + 0.3 v input low voltage ( * 1,2) v il -0.5 ( * 1) 0.8 v operating current (internal) i ccint vccio = 3.5 v, vccint = 1.6 v, masterclock = 100 mhz pclock = 200 mhz 350 550 ma operating current (i/o) i ccio vccio = 3.5 v, vccint = 1.6 v, masterclock = 100 mhz pclock = 200 mhz 50 60 ma input leakage i li except ( * 3) port 10 a pull-up ( * 3) rinu 30 50 100 k ? pull-down ( * 4) rind 30 50 100 k ? output leakage i lo 20 a input capacitance c in 10 pf output capacitance c out 10 pf ( * 1) v il min = ? 1.5 v for pulse width less than 10 ns. ( * 2) except for masterclock input ( * 3) applies to int(5:0) * , nmi * , reset * , jtms, jtck, jtdi, tpc1 inputs ( * 4) applies to trst * , rdrdy * , tpc3, tpc2 inputs 10.1.4 ac characteristics 10.1.4.1 clock timing t c = 0 c to 70 c, vccint = 1.5 v 0.1 v, vccio = 3.3 v 0.2 v parameter symbol conditions min max units masterclock high t mch transition 5 ns 3.0 ns masterclock low t mcl transition 5 ns 3.0 ns masterclock frequency ( * 1) f mck 20 100 mhz internal operation frequency f pck 50 200 mhz masterclock period t mcp 10 50 ns masterclock rise time t mcr 2.0 ns masterclock fall time t mcf 2.0 ns ( * 1) operation of tmpr4955af is only guaranteed with the phase lock loop enabled. ( * 2) all output timings assume a 25 pf capacitive load. output timings should be derated where appropriate. 10.1.4.2 system interface t c = 0 c to 70 c, vccint = 1.5 v 0.1 v, vccio = 3.3 v 0.2 v, bufsel = 100% parameter symbol min max units data output ( * 1, 2, 3) t do 1.0 6.5 ns data setup ( * 3) t ds 3.5 ns data hold ( * 3) tdh 1.0 ns ( * 1) timings are measured from 1.5 v of the masterclock to 1.5 v of signal. ( * 2) capacitive load for all output timings is 25 pf. ( * 3) data output, data setup and data hold apply to all logic signals driven out of or driven into the tmpr4955af on the system interface. clocks are specified separately.
chapter 10 electrical characteristics 10-3 10.1.5 timing diagrams 10.1.5.1 clock timing 10.1.5.2 pclock to sclock divisor of 2 t mch t mcl masterclock 0.8 * v cc io 0.2 * v cc io t mcr t mcf t mcp cycle pclock ( internal si g nal ) sclock (internal signal) sysad driven sysad received 3 2 1 d t ds 4 d d d masterclock d d d d t dh t do
chapter 10 electrical characteristics 10-4 10.1.5.3 system interface timing 10.1.5.4 cold reset timing 10.1.5.5 warm reset timing sclock ( internal si g nal ) sysad syscmd sysadc syscmdp validout * , release * validln * , extrqst * , wrrdy * , rdrdy * , int (5:0) * , nmi * v a lid ou t pu t d masterclock t ds t dh v a lid i npu t t do t ds t dh v a lid input t do t dh divmode (1:0) reset * coldreset * masterclock t ds t dh more than 64,000 masterclock cycles more than 16 masterclock cycles t ds t dh reset * coldreset * masterclock more than 16 masterclock cycles t ds t dh t ds
chapter 11 package dimension 11-1 chapter 11. package dimension qfp160-p-2828-0.65a unit: mm
chapter 11 package dimension 11-2
appendix a. a-1 a. pll passive components the phase locked loop circuit requires several passive components for proper operation, which are connected to vccpll, and vsspll, as illustrated in figure a.1. figure a.1 pll recommended circuit value s: ? r = 5 ? ( * 1) ? c1 = 1 nf ( * 1) ? c2 = 82 nf ( * 1) ? c3 = 10 f ( * 1) ? vccint = 1.5 v 0.1 v the inductors (l) can be used as alternatives to the resistors (r) to filter the power supply. it is essential to isolate the analog power and ground for the pll circuit (vccpll/vsspll) from the regular power and ground (vccint/vss). tx4955a vccint vccpll pllcap ( reserved ) vsspll vss c1 c2 c3 r l c1, c2, c3, r and l are board components which should be placed as close as possible to the processor. r l
appendix a. a-2
appendix b. b-1 b. movement parameter setting of a processor a table explains movement parameter with a processor. item description single write protocol these modes are selected by g2sconfig-register. writeback data rate these modes are selected by g2sconfig-register. clock multiplier these modes are selected by external pin (divmode (1:0)) endian set endian is selected by external pin (endian). indicates the initial setting of the endian during areset. 0: little endian 1: big endian timer interrupt timer-interrupt is selected by external pin (tintdis). it is selection of timer-interrupt or int5. 0: timer-interrupt enable int5 is disable 1: timer-interrupt disable int5 is enable sysad bus protocol type sysad bus protocol type is selected by external pin (mode43 * ). it is selection of tx4300 type or r5000 type. 0: tx4300 type 1: r5000 type note1: a: address (32 bit), w: word (32 bit) note2: initial set of data rate single write: awxx (r4000 compatible) block write: awwwwwwww write mode 00 r4000 compatible awxx 01 reserved reserved 10 reissue write aw 11 pipeline write aw date rate 0 awwwwwwww 1 awxxwxxwxxwxxwxxwxxwxxwxx divmode (1:0) master clock pclock ratio 00 41.8 mhz/50 mhz 167 mhz/200 mhz 1:4 01 66.8 mhz/80 mhz 167 mhz/200 mhz 1:2.5 10 83.5 mhz/100 mhz 167 mhz/200 mhz 1:2 11 55.7 mhz/66 mhz 167 mhz/200 mhz 1:3
appendix b. b-2
appendix c. c-1 c. differences between the tmpr4955 and the tmpr4955a product name tmpr4955f tmpr4955af power supply: core (incl. pll) i/o 2.5 v 3.3 v 1.5 v 3.3 v pin assignment (no.2) (no.35) vccio vccio bufsel1 bufsel0 i/o buffer drive (ratio) 1.0 selectable from 0.5, 1.0 and 1.5 note: bufsel (1:0) = 11 10 01 00 output drive ratio = 100% 150% reserved 50% signals influenced by bufsel(1:0) signal name i/o sysad(31:0) i/o syscmd(8:0) i/o sysadc i/o syscmdp i/o validout * o release * o haltdoze o
appendix c. c-2

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